J-Link WiFi V1

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Revision as of 09:25, 10 August 2022 by Leon (talk | contribs) (Hardware and Software Features)
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This page contains the general, mechanical and electrical specifications as well as an overview of supported soft- and hardware features of the SEGGER J-Link WiFi V1.

Hardware and Software Features

Hardware version 1
Hardware Features
USB 2.0 Full Speed YES.png
USB 2.0 Hi-Speed YES.png
WinUSB YES.png
JTAG interface YES.png
cJTAG interface YES.png
cJTAG interface without/buggy KEEPER logic YES.png
SWD interface YES.png
SWO interface YES.png
SPI interface YES.png
QSPI interface NO.png
Microchip ICSP interface YES.png
Renesas FINE interface YES.png
SiLabs C2 2-wire interface YES.png
ETB Trace ARM7/9 YES.png
ETB Trace Cortex-M YES.png
ETB Trace Cortex-A/R YES.png
ETM Trace Cortex-M NO.png
Memory Stop mode support YES.png
Cortex-M Monitor Mode debugging YES.png
SWD Multi-Drop YES.png
CMSIS-DAP mode YES.png
ARM legacy Cores
ARM7 YES.png
ARM9 YES.png
ARM11 YES.png
ARM Cortex Cores
Cortex-A5 YES.png
Cortex-A7 YES.png
Cortex-A8 YES.png
Cortex-A9 YES.png
Cortex-A12 YES.png
Cortex-A15 YES.png
Cortex-A17 YES.png
Cortex-A53 YES.png
Cortex-A57 YES.png
Cortex-A72 YES.png
Cortex-M0 YES.png
Cortex-M0+ YES.png
Cortex-M1 YES.png
Cortex-M3 YES.png
Cortex-M4 YES.png
Cortex-M7 YES.png
Cortex-M23 YES.png
Cortex-M33 YES.png
Cortex-M85 YES.png
Cortex-R4 YES.png
Cortex-R5 YES.png
Cortex-R8 YES.png
SC000 (M0 secure) YES.png
SC300 (M3 secure) YES.png
RV32 YES.png
RV64 YES.png
Microchip PIC32
SiLabs 8051
EFM8 YES.png
Renesas RX
RX110 YES.png
RX111 YES.png
RX140 YES.png
RX210 YES.png
RX21A YES.png
RX220 YES.png
RX610 YES.png
RX621 YES.png
RX62G YES.png
RX62G YES.png
RX62N YES.png
RX62T YES.png
RX630 YES.png
RX631 YES.png
RX63N YES.png
RX63T YES.png
RX64M YES.png
RX660 YES.png
HiFi 1 YES.png
HiFi 3 YES.png
HiFi 3z YES.png
HiFi 4 YES.png
Fusion F1 YES.png