Difference between revisions of "J-Trace PRO Cortex-M V1"

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(Created page with "This page contains the general, mechanical and electrical specifications as well as an overview of supported soft- and hardware features of the SEGGER '''J-Trace PRO Cortex-M...")
 
(→‎Hardware and Software Features)
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|colspan="7"| Hardware Features
  
|colspan="7"| Hardware Features
 
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|-
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! style="text-align:left;"|USB 2.0 Hi-Speed
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! style="text-align:left;"|USB 2.0 Hi-Speed || {{YES}}
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| [[File:YES.png|20px|link=]]
  
 
|-
  
|-
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! style="text-align:left;"|USB 3.0 SuperSpeed
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! style="text-align:left;"|USB 3.0 SuperSpeed || {{NO}}
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| [[File:NO.png|20px|link=]]
  
 
|-
  
|-
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! style="text-align:left;"|Gigabit-Ethernet
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! style="text-align:left;"|Gigabit-Ethernet || {{YES}}
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| [[File:YES.png|20px|link=]]
  
 
|-
  
|-
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! style="text-align:left;"|cJTAG interface
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! style="text-align:left;"|cJTAG interface || {{NO}}
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| [[File:NO.png|20px|link=]]
  
 
|-
  
|-
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! style="text-align:left;"|JTAG interface
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! style="text-align:left;"|JTAG interface || {{YES}}
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| [[File:YES.png|20px|link=]]
  
 
|-
  
|-
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! style="text-align:left;"|SWD interface
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! style="text-align:left;"|SWD interface || {{YES}}
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| [[File:YES.png|20px|link=]]
  
 
|-
  
|-
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! style="text-align:left;"|SWO interface
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! style="text-align:left;"|SWO interface || {{YES}}
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| [[File:YES.png|20px|link=]]
  
 
|-
  
|-
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! style="text-align:left;"|ETB Trace Cortex-M
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! style="text-align:left;"|ETB Trace Cortex-M || {{YES}}
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| [[File:YES.png|20px|link=]]
  
 
|-
  
|-
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! style="text-align:left;"|ETM Trace Cortex-M
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! style="text-align:left;"|ETM Trace Cortex-M || {{YES}}
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| [[File:YES.png|20px|link=]]
  
 
|-
  
|-
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! style="text-align:left;"|Streaming Trace
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! style="text-align:left;"|Streaming Trace || {{YES}}
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| [[File:YES.png|20px|link=]]
  
 
|-
  
|-
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! style="text-align:left;"|VCOM
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! style="text-align:left;"|VCOM || {{NO}}
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| [[File:NO.png|20px|link=]]
  
 
|-
  
|-
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! style="text-align:left;"|Memory Stop mode support
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! style="text-align:left;"|Memory Stop mode support || {{YES}}
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| [[File:YES.png|20px|link=]]
  
 
|-
  
|-
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! style="text-align:left;"|Cortex-M Monitor Mode debugging
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! style="text-align:left;"|Cortex-M Monitor Mode debugging || {{YES}}
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| [[File:YES.png|20px|link=]]
  
 
|-
  
|-
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! style="text-align:left;"|5 V Target Supply
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! style="text-align:left;"|5 V Target Supply || {{NO}}
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| [[File:NO.png|20px|link=]]
  
 
|-
  
|-
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! style="text-align:left;"|SWD Multi-Drop
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! style="text-align:left;"|SWD Multi-Drop || {{YES}}
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| [[File:YES.png|20px|link=]]
  
 
|-
  
|-
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! style="text-align:left;"|CMSIS-DAP mode
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! style="text-align:left;"|CMSIS-DAP mode || {{NO}}
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| [[File:NO.png|20px|link=]]
  
   
 
|- style="text-align:center"
  
|- style="text-align:center"
 
|colspan="7"| ARM Cortex Cores
  
|colspan="7"| ARM Cortex Cores
 
|-
  
|-
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! style="text-align:left;"|Cortex-A53
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! style="text-align:left;"|Cortex-A53 || {{NO}}
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| [[File:NO.png|20px|link=]]
  
 
|-
  
|-
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! style="text-align:left;"|Cortex-A57
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! style="text-align:left;"|Cortex-A57 || {{NO}}
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| [[File:NO.png|20px|link=]]
  
 
|-
  
|-
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! style="text-align:left;"|Cortex-A72
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! style="text-align:left;"|Cortex-A72 || {{NO}}
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| [[File:NO.png|20px|link=]]
  
 
|-
  
|-
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! style="text-align:left;"|Cortex-M0
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! style="text-align:left;"|Cortex-M0 || {{YES}}
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| [[File:YES.png|20px|link=]]
  
 
|-
  
|-
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! style="text-align:left;"|Cortex-M0+
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! style="text-align:left;"|Cortex-M0+ || {{YES}}
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| [[File:YES.png|20px|link=]]
  
 
|-
  
|-
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! style="text-align:left;"|Cortex-M1
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! style="text-align:left;"|Cortex-M1 || {{YES}}
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| [[File:YES.png|20px|link=]]
  
 
|-
  
|-
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! style="text-align:left;"|Cortex-M3
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! style="text-align:left;"|Cortex-M3 || {{YES}}
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| [[File:YES.png|20px|link=]]
  
 
|-
  
|-
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! style="text-align:left;"|Cortex-M4
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! style="text-align:left;"|Cortex-M4 || {{YES}}
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| [[File:YES.png|20px|link=]]
  
 
|-
  
|-
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! style="text-align:left;"|Cortex-M7
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! style="text-align:left;"|Cortex-M7 || {{YES}}
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| [[File:YES.png|20px|link=]]
  
 
|-
  
|-
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! style="text-align:left;"|Cortex-M23
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! style="text-align:left;"|Cortex-M23 || {{YES}}
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| [[File:YES.png|20px|link=]]
  
 
|-
  
|-
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! style="text-align:left;"|Cortex-M33
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! style="text-align:left;"|Cortex-M33 || {{YES}}
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| [[File:YES.png|20px|link=]]
  
 
|-
  
|-
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! style="text-align:left;"|SC000 (M0 secure)
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! style="text-align:left;"|SC000 (M0 secure) || {{YES}}
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| [[File:YES.png|20px|link=]]
  
 
|-
  
|-
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! style="text-align:left;"|SC300 (M3 secure)
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! style="text-align:left;"|SC300 (M3 secure) || {{YES}}
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| [[File:YES.png|20px|link=]]
  
 
|-
  
|-
 
|- style="text-align:center"
  
|- style="text-align:center"
 
|colspan="7"| RISC-V
  
|colspan="7"| RISC-V
 
|-
  
|-
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! style="text-align:left;"|RV32
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! style="text-align:left;"|RV32 || {{NO}}
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| [[File:NO.png|20px|link=]]
  
 
|-
  
|-
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! style="text-align:left;"|RV64
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! style="text-align:left;"|RV64 || {{NO}}
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| [[File:NO.png|20px|link=]]
  
 
|}
  
|}

Revision as of 15:22, 10 December 2021

This page contains the general, mechanical and electrical specifications as well as an overview of supported soft- and hardware features of the SEGGER J-Trace PRO Cortex-M V1.

Note:

The J-Trace PRO Cortex-M V1 has been superseded and as such is considered a legacy device. This device is not eligible for support by SEGGER.

Refer to the J-Link Model Overview for a list of most recent devices by SEGGER.


Hardware and Software Features

Hardware version 1
Hardware Features
USB 2.0 Hi-Speed YES.png
USB 3.0 SuperSpeed NO.png
Gigabit-Ethernet YES.png
cJTAG interface NO.png
JTAG interface YES.png
SWD interface YES.png
SWO interface YES.png
ETB Trace Cortex-M YES.png
ETM Trace Cortex-M YES.png
Streaming Trace YES.png
VCOM NO.png
Memory Stop mode support YES.png
Cortex-M Monitor Mode debugging YES.png
5 V Target Supply NO.png
SWD Multi-Drop YES.png
CMSIS-DAP mode NO.png
ARM Cortex Cores
Cortex-A53 NO.png
Cortex-A57 NO.png
Cortex-A72 NO.png
Cortex-M0 YES.png
Cortex-M0+ YES.png
Cortex-M1 YES.png
Cortex-M3 YES.png
Cortex-M4 YES.png
Cortex-M7 YES.png
Cortex-M23 YES.png
Cortex-M33 YES.png
SC000 (M0 secure) YES.png
SC300 (M3 secure) YES.png
RISC-V
RV32 NO.png
RV64 NO.png
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