Difference between revisions of "J-Trace PRO Cortex V3"

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(Undo revision 13815 by Fabian (talk))
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This page contains the general, mechanical and electrical specifications as well as an overview of supported soft- and hardware features of the SEGGER '''J-Trace PRO for Cortex-M V3'''.
 +
This page contains the general, mechanical and electrical specifications as well as an overview of supported soft- and hardware features of the SEGGER '''J-Trace PRO for Cortex V3'''.
   
 
__TOC__
  
__TOC__
   
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== Hardware Features ==
 +
== Hardware and Software Features ==
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{| class="seggertable"
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{| class="wikitable"
  +
|+
 
|-
  
|-
  +
! style="position:sticky; top:0"|Hardware version
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! Feature !! Supported
  
  +
! style="position:sticky; top:0"|3
  +
|- style="text-align:center"
  +
|colspan="7"| Hardware Features
 
|-
  
|-
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| USB 2.0 Hi-Speed ||style="text-align:center;"| {{YES}}
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! style="text-align:left;"|USB 2.0 Hi-Speed || {{YES}}
 
|-
  
|-
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| USB 3.0 SuperSpeed ||style="text-align:center;"| {{YES}}
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! style="text-align:left;"|USB 3.0 SuperSpeed || {{YES}}
 
|-
  
|-
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| WinUSB ||style="text-align:center;"| {{YES}}
 +
! style="text-align:left;"|WinUSB || {{YES}}
 
|-
  
|-
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| Gigabit-Ethernet ||style="text-align:center;"| {{YES}}
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! style="text-align:left;"|Gigabit-Ethernet || {{YES}}
 
|-
  
|-
−
| cJTAG interface ||style="text-align:center;"| {{YES}}
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! style="text-align:left;"|cJTAG interface || {{YES}}
 
|-
  
|-
−
| cJTAG interface without/buggy KEEPER logic ||style="text-align:center;"| {{YES}}
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! style="text-align:left;"|cJTAG interface without/buggy KEEPER logic || {{YES}}
 
|-
  
|-
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| JTAG interface ||style="text-align:center;"| {{YES}}
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! style="text-align:left;"|JTAG interface || {{YES}}
 
|-
  
|-
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| SWD interface ||style="text-align:center;"| {{YES}}
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! style="text-align:left;"|SWD interface || {{YES}}
 
|-
  
|-
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| SWO interface ||style="text-align:center;"| {{YES}}
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! style="text-align:left;"|SWO interface || {{YES}}
 
|-
  
|-
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| ETB Trace Cortex-M ||style="text-align:center;"| {{YES}}
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! style="text-align:left;"|ETB Trace Cortex || {{YES}}
 
|-
  
|-
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| ETM Trace Cortex-M ||style="text-align:center;"| {{YES}}
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! style="text-align:left;"|ETM Trace Cortex || {{YES}}
 
|-
  
|-
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| Streaming Trace ||style="text-align:center;"| {{YES}}
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! style="text-align:left;"|PTM Trace Cortex || {{YES}}
 
|-
  
|-
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| VCOM ||style="text-align:center;"| {{NO}}
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! style="text-align:left;"|Streaming Trace || {{YES}}
 
|-
  
|-
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| Memory Stop mode support ||style="text-align:center;"| {{YES}}
 +
! style="text-align:left;"|VCOM || {{NO}}
 
|-
  
|-
−
| Cortex-M Monitor Mode debugging ||style="text-align:center;"| {{YES}}
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! style="text-align:left;"|Memory Stop mode support || {{YES}}
 
|-
  
|-
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| 5 V Target Supply ||style="text-align:center;"| {{YES}}
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! style="text-align:left;"|Cortex-M Monitor Mode debugging || {{YES}}
 
|-
  
|-
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| SWD Multi-Drop ||style="text-align:center;"| {{YES}}
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! style="text-align:left;"|5 V Target Supply || {{YES}}
 
|-
  
|-
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| CMSIS-DAP mode ||style="text-align:center;"| {{NO}}
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! style="text-align:left;"|SWD Multi-Drop || {{YES}}
−
|}
  
−  
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== Supported cores ==
  
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J-Trace provides debugging support for the following cores.<br>
  
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{{Note|1=If you are interested in J-Trace support for a core that is not listed here, please feel free to request support via the [https://www.segger.com/ticket SEGGER support ticket system].}}
  
−  
−
{| class="seggertable"
  
−
|-
  
−
! Core !! Supported
  
 
|-
  
|-
  +
! style="text-align:left;"|CMSIS-DAP mode || {{NO}}
−
!colspan="2"| ARM Cortex Cores
  
  +
|- style="text-align:center"
  +
|colspan="7"| ARM Cortex Cores
 
|-
  
|-
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| Cortex-A5 ||style="text-align:center;"| {{YES}}
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! style="text-align:left;"|Cortex-A5 || {{YES}}
 
|-
  
|-
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| Cortex-A7 ||style="text-align:center;"| {{YES}}
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! style="text-align:left;"|Cortex-A7 || {{YES}}
 
|-
  
|-
−
| Cortex-A8 ||style="text-align:center;"| {{YES}}
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! style="text-align:left;"|Cortex-A8 || {{YES}}
 
|-
  
|-
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| Cortex-A9 ||style="text-align:center;"| {{YES}}
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! style="text-align:left;"|Cortex-A9 || {{YES}}
 
|-
  
|-
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| Cortex-A12 ||style="text-align:center;"| {{YES}}
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! style="text-align:left;"|Cortex-A12 || {{YES}}
 
|-
  
|-
−
| Cortex-A15 ||style="text-align:center;"| {{YES}}
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! style="text-align:left;"|Cortex-A15 || {{YES}}
 
|-
  
|-
−
| Cortex-A17 ||style="text-align:center;"| {{YES}}
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! style="text-align:left;"|Cortex-A17 || {{YES}}
 
|-
  
|-
−
| Cortex-A53 ||style="text-align:center;"| {{NO}}
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! style="text-align:left;"|Cortex-A53 || {{NO}}
 
|-
  
|-
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| Cortex-A55 ||style="text-align:center;"| {{NO}}
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! style="text-align:left;"|Cortex-A55 || {{NO}}
 
|-
  
|-
−
| Cortex-A57 ||style="text-align:center;"| {{NO}}
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! style="text-align:left;"|Cortex-A57 || {{NO}}
 
|-
  
|-
−
| Cortex-A72 ||style="text-align:center;"| {{NO}}
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! style="text-align:left;"|Cortex-A72 || {{NO}}
 
|-
  
|-
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| Cortex-R4 ||style="text-align:center;"| {{YES}}
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! style="text-align:left;"|Cortex-R4 || {{YES}}
 
|-
  
|-
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| Cortex-R5 ||style="text-align:center;"| {{YES}}
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! style="text-align:left;"|Cortex-R5 || {{YES}}
 
|-
  
|-
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| Cortex-R8 ||style="text-align:center;"| {{YES}}
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! style="text-align:left;"|Cortex-R8 || {{YES}}
 
|-
  
|-
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| Cortex-M0 ||style="text-align:center;"| {{YES}}
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! style="text-align:left;"|Cortex-M0 || {{YES}}
 
|-
  
|-
−
| Cortex-M0+ ||style="text-align:center;"| {{YES}}
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! style="text-align:left;"|Cortex-M0+ || {{YES}}
 
|-
  
|-
−
| Cortex-M1 ||style="text-align:center;"| {{YES}}
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! style="text-align:left;"|Cortex-M1 || {{YES}}
 
|-
  
|-
−
| Cortex-M3 ||style="text-align:center;"| {{YES}}
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! style="text-align:left;"|Cortex-M3 || {{YES}}
 
|-
  
|-
−
| Cortex-M4 ||style="text-align:center;"| {{YES}}
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! style="text-align:left;"|Cortex-M4 || {{YES}}
 
|-
  
|-
−
| Cortex-M7 ||style="text-align:center;"| {{YES}}
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! style="text-align:left;"|Cortex-M7 || {{YES}}
 
|-
  
|-
−
| Cortex-M23 ||style="text-align:center;"| {{YES}}
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! style="text-align:left;"|Cortex-M23 || {{YES}}
 
|-
  
|-
−
| Cortex-M33 ||style="text-align:center;"| {{YES}}
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! style="text-align:left;"|Cortex-M33 || {{YES}}
 
|-
  
|-
−
| Cortex-M85 ||style="text-align:center;"| {{YES}}
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! style="text-align:left;"|Cortex-M85 || {{YES}}
 
|-
  
|-
−
| SC000 (M0 secure) ||style="text-align:center;"| {{YES}}
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! style="text-align:left;"|SC000 (M0 secure) || {{YES}}
 
|-
  
|-
−
| SC300 (M3 secure) ||style="text-align:center;"| {{YES}}
 +
! style="text-align:left;"|SC300 (M3 secure) || {{YES}}
 
|-
  
|-
  +
|- style="text-align:center"
−
!colspan="2"| RISC-V
  
  +
|colspan="7"| RISC-V
 
|-
  
|-
−
| RV32 ||style="text-align:center;"| {{NO}}
 +
! style="text-align:left;"|RV32 || {{NO}}
 
|-
  
|-
−
| RV64 ||style="text-align:center;"| {{NO}}
 +
! style="text-align:left;"|RV64 || {{NO}}
 
|}
  
|}

Revision as of 16:21, 20 December 2022

This page contains the general, mechanical and electrical specifications as well as an overview of supported soft- and hardware features of the SEGGER J-Trace PRO for Cortex V3.

Hardware and Software Features

Hardware version 3
Hardware Features
USB 2.0 Hi-Speed YES.png
USB 3.0 SuperSpeed YES.png
WinUSB YES.png
Gigabit-Ethernet YES.png
cJTAG interface YES.png
cJTAG interface without/buggy KEEPER logic YES.png
JTAG interface YES.png
SWD interface YES.png
SWO interface YES.png
ETB Trace Cortex YES.png
ETM Trace Cortex YES.png
PTM Trace Cortex YES.png
Streaming Trace YES.png
VCOM NO.png
Memory Stop mode support YES.png
Cortex-M Monitor Mode debugging YES.png
5 V Target Supply YES.png
SWD Multi-Drop YES.png
CMSIS-DAP mode NO.png
ARM Cortex Cores
Cortex-A5 YES.png
Cortex-A7 YES.png
Cortex-A8 YES.png
Cortex-A9 YES.png
Cortex-A12 YES.png
Cortex-A15 YES.png
Cortex-A17 YES.png
Cortex-A53 NO.png
Cortex-A55 NO.png
Cortex-A57 NO.png
Cortex-A72 NO.png
Cortex-R4 YES.png
Cortex-R5 YES.png
Cortex-R8 YES.png
Cortex-M0 YES.png
Cortex-M0+ YES.png
Cortex-M1 YES.png
Cortex-M3 YES.png
Cortex-M4 YES.png
Cortex-M7 YES.png
Cortex-M23 YES.png
Cortex-M33 YES.png
Cortex-M85 YES.png
SC000 (M0 secure) YES.png
SC300 (M3 secure) YES.png
RISC-V
RV32 NO.png
RV64 NO.png
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