Difference between revisions of "Kinetis KE1xZ 48 MHz series"
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[https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPackBeta Download latest version] |
[https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPackBeta Download latest version] |
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− | = |
+ | = Watchdog support = |
+ | Debugging and flash programming with the watchdog (WDOG) being enabled (in non-windowed mode) is supported. Windowed mode of the watchdog is not supported for debugging and flash programming. |
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− | The cores are named as follows: |
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+ | = MTB trace = |
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− | {| class="wikitable" |
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+ | The KE1xZ 48 MHz series devices incorporate an ARM MTB on-chip trace buffer that allows instruction backtrace. For more information about MTB in general, please refer to [[MTB_specifics | here]]. |
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− | !Core name |
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− | !Description |
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− | |- |
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− | |Cortex-M33 (core 0) |
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− | |Main core that device boots from by default |
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− | |- |
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− | |Cortex-M33 (core 1) |
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− | |Secondary core that is not booted by default on reset release |
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− | |} |
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− | |||
− | == J-Link device selection == |
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− | The following device names are available for J-Link: |
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− | |||
− | {| class="wikitable" |
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− | !Device name |
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− | !Function |
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− | |- |
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− | |SSE-200-MPS3 |
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− | |Connects to core 0 |
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− | |- |
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− | |SSE-200-MPS3_M33_0 |
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− | |Connects to core 0 |
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− | |- |
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− | |SSE-200-MPS3_M33_1 |
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− | |Connects to core 1. Core 1 is enabled (released from reset) automatically by J-Link, if necessary |
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− | |} |
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= Example projects = |
= Example projects = |
Revision as of 10:47, 25 September 2018
Contents
The NXP Kinetis KE1xZ 48 MHz series is deigned for white goods and industrial applications. It incorporates an ARM Cortex-M0+ core.
J-Link support
The KE14Z32, KE14Z64, KE15Z32, KE15Z64, KE16Z32, KE16Z64 are supported in V6.35g and later versions of the J-Link software.
Watchdog support
Debugging and flash programming with the watchdog (WDOG) being enabled (in non-windowed mode) is supported. Windowed mode of the watchdog is not supported for debugging and flash programming.
MTB trace
The KE1xZ 48 MHz series devices incorporate an ARM MTB on-chip trace buffer that allows instruction backtrace. For more information about MTB in general, please refer to here.
Example projects
There are sample projects available that demonstrate how to use J-Link with the ARM CoreLink SSE-200 prototyping platform.
SEGGER Embedded Studio (multi-core)
The sample project for SEGGER Embedded Studio is a RAM based project and also demonstrates multi-core debugging. The sample is actually split into 2 projects:
ARM_SSE-200-MPS3_MPS3_LEDBlinkCore0_ES
Loaded into internal SRAM and executed by core 0. Controls LED1 and LED2 on the MPS3 board. LED1 is always toggled, LED2 is toggled as long as core 1 is running its application and sending commands to core 0
ARM_SSE-200-MPS3_MPS3_LEDBlinkCore1_ES
Loaded into internal SRAM and executed by core 1. Sends commands to core 0 that instruct the main application to toggle LED2
Usage
- Start SEGGER Embedded Studio twice
- Open ARM_SSE-200-MPS3_MPS3_LEDBlinkCore0_ES and ARM_SSE-200-MPS3_MPS3_LEDBlinkCore1_ES accordingly
- Start debug session with project for core 0
- Let CPU run as soon as main() has hit
- Start debug session with project for core 1
- Let CPU run as soon as main() has hit
- LED1 and LED2 will blink
- Now halt core 1 (issue halt request in debug session for core 1)
- LED2 stops blinking, LED1 continues to blink
Requirements
The following are the min. requirements to run the example project:
- SEGGER Embedded Studio V3.40 or later
- J-Link software V6.33h or later. (Install after Embedded Studio and let J-Link installer update the Embedded Studio installation)
- ARM MPS3 board