The LPC55xx / LPC55Sxx is an Cortex-M33 based microcontroller for embedded applications including a Cortex-M33 co-processor.
In case some bad code has been flashed into the device (wrong PLL init that bricks the device, ...) that makes it unresponsive to debug commands, there is no built-in mechanism that allows J-Link to regain control over the device, however the device is not lost yet.
LPC55xx / LPC55Sxx series devices provide a specific pin to enter ISP mode on boot which effectively inhibits starting the user application and therefore the bad code. In order to recover an LPC55xx / LPC55Sxx series device that is running bad code, the following needs to be done:
- Short PIO0_5 with GND
- Power-cycle the device (make sure that LOW is sampled on PIO0_5)
- Release PIO0_5
- Start J-Link Commander, J-Flash or any other utility that supports J-Link and reflash the device
NOTE: On the LPC55S69-EVK there is a separate "ISP" button which can be used for this purpose.
To be able to use the SWO pin, target specific steps have to be executed. The following pins can be initialized as SWO pins:
Since V6.63b of the J-Link Software and Documentation Pack, SWO for PIO0_10 is supported and works out-of-the-box. If you want to use PIO0_08 as SWO pin, please contact SEGGER support via Support Ticket System.
SWO sample project
The following SWO sample project was tested on the NXP LPCXpresso55S69 evaluation board:
- J-Link DLL V6.63b or later
- SEGGER Embedded Studio for ARM V4.42 or later
- Any J-Link or J-Trace with SWO support
NXP LPC55S6x series
The LPC55S6x devices contain two Cortex-M33 cores, one main and one co-processor. Both cores are supported by the J-Link Software and Documentation Pack.
Debug support for the second Cortex-M33 (co-processor) is part of the J-Link Software and Documentation Pack V6.88 and above.
Unlike as for the main Cortex-M33, flash-programming is currently not supported for the second Cortex-M33 (co-processor).