Difference between revisions of "Microchip SAMD21"
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Pushing reset buttons that may be present on the target HW is not supported while there is an active debug connection with J-Link. Reason for this is the SAMD21 specific feature called "reset extension phase". The reset extension phase is a special feature of the SAMD21 series that holds the core in reset if the SWCLK pin is sampled logic 0 (LOW) after the reset pin is released. Since J-Link may be permanently communicating with the device in the background while there is an active debug connection, there is constant activity on the SWCLK pin. So there is a 50% chance that the SWCLK pin is LOW when the user releases the reset button on the board. If the device enters the reset extension phase, the core is kept in reset and the target application does not start. |
Pushing reset buttons that may be present on the target HW is not supported while there is an active debug connection with J-Link. Reason for this is the SAMD21 specific feature called "reset extension phase". The reset extension phase is a special feature of the SAMD21 series that holds the core in reset if the SWCLK pin is sampled logic 0 (LOW) after the reset pin is released. Since J-Link may be permanently communicating with the device in the background while there is an active debug connection, there is constant activity on the SWCLK pin. So there is a 50% chance that the SWCLK pin is LOW when the user releases the reset button on the board. If the device enters the reset extension phase, the core is kept in reset and the target application does not start. |
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Latest revision as of 15:57, 21 January 2020
Contents
Reset buttons on target hardware
Pushing reset buttons that may be present on the target HW is not supported while there is an active debug connection with J-Link. Reason for this is the SAMD21 specific feature called "reset extension phase". The reset extension phase is a special feature of the SAMD21 series that holds the core in reset if the SWCLK pin is sampled logic 0 (LOW) after the reset pin is released. Since J-Link may be permanently communicating with the device in the background while there is an active debug connection, there is constant activity on the SWCLK pin. So there is a 50% chance that the SWCLK pin is LOW when the user releases the reset button on the board. If the device enters the reset extension phase, the core is kept in reset and the target application does not start.
