NXP RD-RW616-BGA IPA-2A/1A

From SEGGER Wiki
Revision as of 13:20, 15 May 2024 by Simon Buchholz (talk | contribs)
(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)
Jump to navigation Jump to search

This article describes specifics for the NXP RD-RW616-BGA_IPA-2A/1A evaluation board.
NXP RD-RW612-BGA RW612EV board.jpg

Preparing for J-Link

  • Power the board via J1
  • Jumper JP1 must be set in order to use J-Link

For use of SWD:

    • HD12 1-2 has to be closed (RF_CNTL_2/CON[11])
    • Connect JLINK to P2 (SWD)

For use of JTAG:

    • HD12 1-2 has to be open (RF_CNTL_2/CON[11])
    • Connect JLINK to J19 (JTAG)
  • Verify the Connection with e.g. J-Link Commander. The output should look as follows:

NXP RD-RW612-BGA RW612EV connect.png

Example Project

The following example project was created with the SEGGER Embedded Studio project wizard and runs out-of-the-box on the NXP RD-RW616-BGA_IPA-2A/1A.
It is a simple Hello World sample linked into the internal flash.

SETUP