This article covers the NXP i.MXRT500 MCU family devices.
The RT500 does not come with internal flash but with external flash connected to the FlexSPI bus, only. The external FlexSPI controller allows to connect several different flash types like QSPI, HyperFlash and Octaflash. Furthermore, the external flash can be connected to different pin / ports of the FlexSPI controller which makes a auto-detection very difficult thus a out-of-the-box solution which works for all setups is kind of impossible. For that reason, the J-Link software supports the evaluation board setup, only. Other setups may work but without any warranty or guarantee from SEGGER. If you are working with a different setup and looking for support for this setup, please get in touch with SEGGER.
Supported QSPI setup
- J-Link Software: >= V6.82a
- Hardware: NXP X-MIMXRT595-EVK (RevC1)
- Flash: MX25UW51345GXDI00 (octaflash) connected to FlexSPI port A1
NOTE: The BOOT ROM of the RT500 seems to activate the octa mode under some circumstances. In order to bring the flash into a proper / known state, the J-Link flashloader resets the QSPI flash using the nRESET pin of the flash which is connected to PIO4_05 on the evaluation board. On some preliminary boards, the reset pin was connected to PIO4_24. These boards do not work with the default flashloader.
The application toggles the red LED on the MIMXRT595-EVK Rev C1 evaluation board. The application is linked into the external flash. It includes a valid boot header so it also runs stand-alone.
- J-Link software: V6.82a
- Embedded Studio: V4.50
- Hardware: NXP MIMXRT595-EVK (Rev C1)
- Link: File:NXP MIMXRT595-EVK-RevC1 QSPI ES.zip
Cadence Tensilica Fusion F1 DSP
The i.MXRT500 devices features a Cadence Tensilica Fusion F1 DSP.
J-Link supports parallel debug sessions with the Cortex-M33 and the Fusion F1 core of the i.MXRT500. The required J-Link software version is V.88j or greater.
Two steps are required to establish the connection to the Fusion F1 core:
- The target application of the Cortex-M33 has to release the Fusion F1 core
- The target application of the Fusion F1 hast to be loaded into memory
A getting started guide by NXP can be found at: https://www.nxp.com/docs/en/supporting-information/GSXEVKMIMXRT595.pdf.
An equivalent example with the i.MXRT600 and the Cadence Tensilica Hifi4 DSP can be found at: https://blog.segger.com/debugging-the-dual-core-nxp-i-mx-rt600-with-the-one-and-only-segger-j-link.
This section covers the NXP i.MXRT595S devices.
The following projects have been tested with the minimum requirements mentioned and a NXP MIMXRT595-EVK Rev C1 evaluation board. In order to rebuild the sample project, SEGGER Embedded Studio can be used.
In order to use trace on the NXP i.MXRT595S devices, the following minimum requirements have to be met:
- J-Link software version V6.80a or later
- Ozone V3.20c or later (if sample project from below shall be used)
- J-Trace PRO for Cortex-M HW version V1.0 or later for streaming trace
The recommended version to rebuild the projects is ES V6.30. But the examples are all pre-build and work out-of-the box with Ozone, so rebuilding is not necessary.
Note: The example is shipped with a compiled .JLinkScriptfile, should you need the original source, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/.
To create your own .JLinkScriptfile you can use the following guide as reference: How_to_configure_JLinkScript_files_to_enable_tracing
Reference trace signal quality
The following pictures show oscilloscope measurements of trace signals output by the "Tested Hardware" using the example project. All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes. If your trace signals look similar on your trace hardware, chances are good that tracing will work out-of-the-box using the example project. More information about correct trace timing can be found at the following website.
The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1. For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal.
The setup time shows the relative setup time between a trace data signal and trace clock. The measurement markers are set at 50% of the expected voltage level respectively. The following picture shows such a measurement for the trace data signal 0 relative to the trace clock signal.
- After flashing an application to an erased i.MXRT500, it has to be reset, so the bootloader can setup the application correctly.
This is done automatically in the sample projects above.