QSPI Flash Programming Support

General Information

More and more CPUs include an so called SPIFI memory controller which allows memory mapped read accesses to any SPI flash, connected to the Quad-SPI interface of the CPU. This allows the J-Link DLL to support flash programming through the Quad-SPI interface of the CPU.

Problem

Some CPUs allow to use different port / pin configurations for the connection of the SPI flash. Thus, for each possible pin / port configuration a slightly different flash algorithm is required, even if the same SPI flash and the same CPU is used.

Solution

For CPUs, which allow to use different port / pin configurations, we create 1-2 example flash algorithms, based on the pin configuration of the evaluation board. If you chose the same pin layout as used on the evaluation board, the flash algorithms can be used out-of-the-box. Information about what needs to be done if a different pin configuration is used can be found below (see Customized Solution Required). The flash algorithms are based on the Open Flashloader concept. This allows customer to easily exchange the used flashloader by replacing the flashloader file referenced by the JLinkDevices.xml.

Customized Solution Required

If there is no example flash algorithm for your port / pin configuration available, the flash algorithm needs to be slightly modified. In general this change effects the pin / port initialization, only. For further information regarding the Open Flashloader and how to use the JLinkDevices.xml file, please refer to the J-Link User Manual (UM08001), chapter 10 Open Flash Loader.

Specific Landing Pages Provide Following Information

• Setup (CPU / board)
• Port / pin configuration
• JLinkDevices.XML
• Files

Overview of Available QSPI Flashloader

• ST
  • STM32F446 (Custom Board)
  • STM32L476 (STM32L476 Discovery)
  • STM32L476 (STM32L476 Eval)
  • STM32F746 (STM32F746 Discovery)
• NXP (Freescale)
  • iMX6SX
  • iMX7UL (MCIMX6UL-EVK)
  • MK80FN256V15 (TWR-K80F150M)