Difference between revisions of "Renesas RA6M3"
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__TOC__ |
__TOC__ |
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| − | =Tracing on RA6M3 series= |
+ | ==Tracing on RA6M3 series== |
This section describes how to get started with trace on the Renesas RA6M3 MCUs. |
This section describes how to get started with trace on the Renesas RA6M3 MCUs. |
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This section assumes that there is already a basic knowledge about trace in general (what is trace, what different implementations of trace are there, etc.). |
This section assumes that there is already a basic knowledge about trace in general (what is trace, what different implementations of trace are there, etc.). |
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* All examples are shipped with a compiled .JLinkScriptfile (.pex), should you need the original source, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/. |
* All examples are shipped with a compiled .JLinkScriptfile (.pex), should you need the original source, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/. |
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| − | == Tracing on Renesas R7FA6M3AH3C == |
+ | === Tracing on Renesas R7FA6M3AH3C === |
| − | === Minimum requirements === |
+ | ==== Minimum requirements ==== |
In order to use trace on the Renesas R7FA6M3AH3C MCU devices, the following minimum requirements have to be met: |
In order to use trace on the Renesas R7FA6M3AH3C MCU devices, the following minimum requirements have to be met: |
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* J-Link software version V6.62 or later |
* J-Link software version V6.62 or later |
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* J-Link Plus V10 or later for ETB trace |
* J-Link Plus V10 or later for ETB trace |
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| − | === Streaming trace === |
+ | ==== Streaming trace ==== |
The project has been tested with the minimum requirements mentioned above and a ''Renesas EK-RA6M3'' evaluation board. |
The project has been tested with the minimum requirements mentioned above and a ''Renesas EK-RA6M3'' evaluation board. |
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'''Example project:''' [[Media:Renesas_R7FA6M3AH_TracePins.zip | Renesas_R7FA6M3AH_TracePins.zip]] |
'''Example project:''' [[Media:Renesas_R7FA6M3AH_TracePins.zip | Renesas_R7FA6M3AH_TracePins.zip]] |
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| − | === Trace buffer (ETB) === |
+ | ==== Trace buffer (ETB) ==== |
'''Example Project:''' [[Media:Renesas_R7FA6M3AH_TraceBuffer.zip | Renesas_R7FA6M3AH_TraceBuffer.zip]] |
'''Example Project:''' [[Media:Renesas_R7FA6M3AH_TraceBuffer.zip | Renesas_R7FA6M3AH_TraceBuffer.zip]] |
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| − | === Tested Hardware === |
+ | ==== Tested Hardware ==== |
[[File:Renesas_EK-RA6M3.png|none|thumb|Renesas EK-RA6M3]] |
[[File:Renesas_EK-RA6M3.png|none|thumb|Renesas EK-RA6M3]] |
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| − | === Reference trace signal quality === |
+ | ==== Reference trace signal quality ==== |
The following pictures show oscilloscope measurements of trace signals output by the "Tested Hardware" using the example project. |
The following pictures show oscilloscope measurements of trace signals output by the "Tested Hardware" using the example project. |
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All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes. |
All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes. |
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More information about correct trace timing can be found at the following [https://www.segger.com/products/debug-probes/j-trace/technology/setting-up-trace/ website]. |
More information about correct trace timing can be found at the following [https://www.segger.com/products/debug-probes/j-trace/technology/setting-up-trace/ website]. |
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| − | ==== Trace clock signal quality ==== |
+ | ===== Trace clock signal quality ===== |
The trace clock signal quality shows multiple trace clock cycles on the tested hardware as reference. |
The trace clock signal quality shows multiple trace clock cycles on the tested hardware as reference. |
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[[File:EK-RA6M3_Multiple_TCLK.png|none|thumb|Trace clock signal quality]] |
[[File:EK-RA6M3_Multiple_TCLK.png|none|thumb|Trace clock signal quality]] |
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| − | ==== Rise time ==== |
+ | ===== Rise time ===== |
The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1. |
The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1. |
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For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal. |
For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal. |
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[[File:EK-RA6M3_Risetime_TCLK.png|none|thumb|TCLK rise time]] |
[[File:EK-RA6M3_Risetime_TCLK.png|none|thumb|TCLK rise time]] |
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| − | ==== Setup time ==== |
+ | ===== Setup time ===== |
The setup time shows the relative setup time between a trace data signal and trace clock. |
The setup time shows the relative setup time between a trace data signal and trace clock. |
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The measurement markers are set at 50% of the expected voltage level respectively. |
The measurement markers are set at 50% of the expected voltage level respectively. |
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Revision as of 18:06, 13 November 2020
This article covers the Renesas RA6M3 Family
Contents
Tracing on RA6M3 series
This section describes how to get started with trace on the Renesas RA6M3 MCUs. This section assumes that there is already a basic knowledge about trace in general (what is trace, what different implementations of trace are there, etc.). If this is not the case, we recommend to read Trace chapter in the J-Link User Manual (UM08001).
Note:
- The sample projects come with a pre-configured project file for Ozone that runs out-of-the box.
- The following sample project is designed to be used with J-Trace PRO for streaming trace, J-Link Plus for buffer tracing (TMC/ETB trace) and Ozone to demonstrate streaming trace.
- In order to rebuild the sample project, SEGGER Embedded Studio can be used.
- All examples are shipped with a compiled .JLinkScriptfile (.pex), should you need the original source, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/.
Tracing on Renesas R7FA6M3AH3C
Minimum requirements
In order to use trace on the Renesas R7FA6M3AH3C MCU devices, the following minimum requirements have to be met:
- J-Link software version V6.62 or later
- Ozone V3.10c or later (if streaming trace and / or the sample project from below shall be used)
- J-Trace PRO for Cortex-M HW version V1.0 or later for streaming trace
- J-Link Plus V10 or later for ETB trace
Streaming trace
The project has been tested with the minimum requirements mentioned above and a Renesas EK-RA6M3 evaluation board.
Example project: Renesas_R7FA6M3AH_TracePins.zip
Trace buffer (ETB)
Example Project: Renesas_R7FA6M3AH_TraceBuffer.zip
Tested Hardware
Reference trace signal quality
The following pictures show oscilloscope measurements of trace signals output by the "Tested Hardware" using the example project. All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes. If your trace signals look similar on your trace hardware, chances are good that tracing will work out-of-the-box using the example project. More information about correct trace timing can be found at the following website.
Trace clock signal quality
The trace clock signal quality shows multiple trace clock cycles on the tested hardware as reference.
Rise time
The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1. For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal.
Setup time
The setup time shows the relative setup time between a trace data signal and trace clock. The measurement markers are set at 50% of the expected voltage level respectively. The following picture shows such a measurement for the trace data signal 0 relative to the trace clock signal.
