Difference between revisions of "Renesas RX66T"
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This article describes device specifics of the Renesas RX66T series microcontrollers. |
This article describes device specifics of the Renesas RX66T series microcontrollers. |
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| + | =Requirements= |
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| − | =Option-setting memory= |
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| + | * J-Link software V6.47e or later: [https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack Download] |
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| − | Programming the option setting memory on .... |
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| + | Programming of the internal code flash, data flash and option-setting memory has been verified with the following J-Flash project and data files: |
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| + | xxxxxxxxxxxxxxxxxxxxxxxx |
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| − | Flash programming of the To program the option bytes starting at address '''0x01010008''', within Synergy device series, |
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| − | it is necessary to program the complete option byte sector starting from address '''0x01010008''' to address '''0x01010033''', also bytes that shall not get modified. |
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| − | In case of programming only parts of the option bytes, the flash algorithm also tries to erase the non-modified bytes within the option byte sector. |
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| − | Due to the fact that certain bits cannot be erased after being programmed once the subsequent verification of the option byte sector fails, when these bits remain '0'. In this case further programming of remaining sections is aborted. |
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| + | =Option-setting memory= |
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| − | == Using SWO on Synergy Devices == |
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| + | Programming the option setting memory at addr. 0x12_0040 is supported. |
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| − | In general, the J-Link DLL expects the trace clock to be equal to the CPU clock. As the Synergy device series allows to enable a pre-scaler which is valid for trace clock only, this assumption may be incorrect resulting in invalid SWO data are read. To make sure that the J-Link DLL behaves as expected, please make sure to not enter the actual CPU clock but the CPU clock multiplied with the ICKdivider configured in the System Clock Division Control Register (SCKDIVCR) divided by the trace clock divider configured in the Trace Clock Control Regigster (TRCKCR). Further information regarding this can be found in the two examples below. |
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| − | ===Example (S3A7)=== |
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| − | *MOCO (8MHz) |
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| − | *System Clock Division Control Register (SCKDIVCR[ICK[2:0]]): 0x4 --> * 1 / 16 |
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| − | *System Clock Source Control Register (SCKSCR[CKSEL[2:0]]): 0x1 --> MOCO selected as source for the ICLK (System Clock) and TRCLK (Trace Clock) |
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| − | *Trace Clock Control Register (TRCKCR[TRCK[3:0]]): 0x1 --> /2 |
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| − | *ICLK = 8MHz * 1 / 16 = 500 kHz CPU clock |
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| − | *TRCLK = ICLK * 1 / 2 = 250 kHz Trace / SWO clock |
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| − | CPU clock to be entered in the IDE project = ICLK * ICKdivider / TRCKdivider = 500 kHz * 16 / 2 = 4 MHz |
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| − | ===Example (S7G2)=== |
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| − | *MOCO (8MHz) |
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| − | *System Clock Division Control Register (SCKDIVCR[ICK[2:0]]): 0x4 --> * 1 / 4 |
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| − | *System Clock Source Control Register (SCKSCR[CKSEL[2:0]]): 0x1 --> MOCO selected as source for the ICLK (System Clock) and TRCLK (Trace Clock) |
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| − | *Trace Clock Control Register (TRCKCR[TRCK[3:0]]): 0x1 --> /2 |
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| − | *ICLK = 8MHz * 1 / 4 = 2 MHz CPU clock |
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| − | *TRCLK = ICLK * 1 / 2 = 1 MHz Trace / SWO clock |
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| + | '''Note:''' Programming of '''UB code A''' and '''UB code B''' in user boot area at 0xFF7F_FFE8 is '''not''' suppored |
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| − | CPU clock to be entered in the IDE project = ICLK * ICKdivider / TRCKdivider = 2 MHz * 4 / 2 = 4 MHz |
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Revision as of 16:35, 3 July 2019
This article describes device specifics of the Renesas RX66T series microcontrollers.
Requirements
- J-Link software V6.47e or later: Download
Programming of the internal code flash, data flash and option-setting memory has been verified with the following J-Flash project and data files:
xxxxxxxxxxxxxxxxxxxxxxxx
Option-setting memory
Programming the option setting memory at addr. 0x12_0040 is supported.
Note: Programming of UB code A and UB code B in user boot area at 0xFF7F_FFE8 is not suppored
