Difference between revisions of "Renesas RZ/G2L"
(→Cortex-M33) |
|||
| Line 9: | Line 9: | ||
==Evaluation Boards== |
==Evaluation Boards== |
||
| − | *Renesas |
+ | *Renesas RZ/G2L SWARC EVK: https://wiki.segger.com/NXP_RZG2L_SWARC_EVK |
==Example Application== |
==Example Application== |
||
| − | *Renesas |
+ | *Renesas RZ/G2L SWARC EVK: https://wiki.segger.com/NXP_RZG2L_SWARC_EVK#Example_Project |
Revision as of 16:37, 4 June 2021
The Renesas RZ/G2L microcontroller features a Cortex-A55 (single or dual) as main processors and a Cortex-M33 as co-processor.
Cores
Cortex-M33
By default, the Cortex-M33 is not enabled / held in reset. The J-Link software executes a device specific initialization sequence which enables the Cortex-M33 thus debugging via Cortex-M33 works out-of-the-box.
Cortex-A55
Not supported yet.
Evaluation Boards
- Renesas RZ/G2L SWARC EVK: https://wiki.segger.com/NXP_RZG2L_SWARC_EVK
Example Application
- Renesas RZ/G2L SWARC EVK: https://wiki.segger.com/NXP_RZG2L_SWARC_EVK#Example_Project
