Difference between revisions of "Renesas RZ/G2L"

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(Created page with "__TOC__ The Renesas RZ/G2L microcontroller features a Cortex-A55 (single or dual) as main processors and a Cortex-M33 as co-processor. ==Cores== ===Cortex-M33=== By default, t...")
 
(Example Application)
 
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==Cores==
 
==Cores==
 
===Cortex-M33===
 
===Cortex-M33===
By default, the Cortex-M33 is not enabled / held in reset. The J-Link software executes a device specific initialization sequence which enables the Cortex-M33 thus allows to debug the core out-of-the-box. Minimum software version: V7.22.
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By default, the Cortex-M33 is not enabled / held in reset. The J-Link software executes a device specific initialization sequence which enables the Cortex-M33 thus debugging via Cortex-M33 works out-of-the-box.
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===Cortex-A55===
 
===Cortex-A55===
 
Not supported yet.
 
Not supported yet.
   
 
==Evaluation Boards==
 
==Evaluation Boards==
*Renesas RZG2L SWARC Module: https://wiki.segger.com/NXP_RZG2L_SWARC_Module
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*Renesas RZ/G2L SMARC EVK: https://wiki.segger.com/Renesas_RZ/G2L_SMARC_EVK
   
 
==Example Application==
 
==Example Application==
*Renesas RZG2L evaluation board: https://wiki.segger.com/NXP_RZG2L_SWARC_Module#Example_Project
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*Renesas RZ/G2L SMARC EVK: https://wiki.segger.com/Renesas_RZ/G2L_SMARC_EVK#Example_Project

Latest revision as of 11:17, 7 June 2021

The Renesas RZ/G2L microcontroller features a Cortex-A55 (single or dual) as main processors and a Cortex-M33 as co-processor.

Cores

Cortex-M33

By default, the Cortex-M33 is not enabled / held in reset. The J-Link software executes a device specific initialization sequence which enables the Cortex-M33 thus debugging via Cortex-M33 works out-of-the-box.

Cortex-A55

Not supported yet.

Evaluation Boards

Example Application