Difference between revisions of "Renesas RZ/G2L"

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==Evaluation Boards==
==Evaluation Boards==
*Renesas RZ/G2L SWARC EVK: https://wiki.segger.com/NXP_RZG2L_SWARC_EVK
*Renesas RZ/G2L SMARC EVK: https://wiki.segger.com/Renesas_RZ/G2L_SMARC_EVK
==Example Application==
==Example Application==
*Renesas RZ/G2L SWARC EVK: https://wiki.segger.com/NXP_RZG2L_SWARC_EVK#Example_Project
*Renesas RZ/G2L SMARC EVK: https://wiki.segger.com/Renesas_RZ/G2L_SMARC_EVK#Example_Project

Latest revision as of 11:17, 7 June 2021

The Renesas RZ/G2L microcontroller features a Cortex-A55 (single or dual) as main processors and a Cortex-M33 as co-processor.



By default, the Cortex-M33 is not enabled / held in reset. The J-Link software executes a device specific initialization sequence which enables the Cortex-M33 thus debugging via Cortex-M33 works out-of-the-box.


Not supported yet.

Evaluation Boards

Example Application