Difference between revisions of "Renesas RZ/G2L"
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==Example Application== |
==Example Application== |
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Revision as of 11:38, 31 May 2021
The Renesas RZ/G2L microcontroller features a Cortex-A55 (single or dual) as main processors and a Cortex-M33 as co-processor.
Cores
Cortex-M33
By default, the Cortex-M33 is not enabled / held in reset. The J-Link software executes a device specific initialization sequence which enables the Cortex-M33 thus allows to debug the core out-of-the-box. Minimum software version: V7.22.
Cortex-A55
Not supported yet.
Evaluation Boards
- Renesas RZG2L SWARC EVK: https://wiki.segger.com/NXP_RZG2L_SWARC_EVK
Example Application
- Renesas RZG2L SWARC EVK: https://wiki.segger.com/NXP_RZG2L_SWARC_EVK#Example_Project
