Difference between revisions of "SIM3L"

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= Tracing on SIM3L-series devices =
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== Tracing on SIM3L-series devices ==
 
This section describes how to get started with trace on the Silicon Labs SIM3L MCUs.
 
This section describes how to get started with trace on the Silicon Labs SIM3L MCUs.
 
This section assumes that there is already a basic knowledge about trace in general (what is trace, what different implementations of trace are there, etc.).
 
This section assumes that there is already a basic knowledge about trace in general (what is trace, what different implementations of trace are there, etc.).
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* All examples are shipped with a compiled .JLinkScriptfile (.pex), should you need the original source, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/.
 
* All examples are shipped with a compiled .JLinkScriptfile (.pex), should you need the original source, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/.
   
== Tracing on SiLabs SIM3L167 ==
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=== Tracing on SiLabs SIM3L167 ===
=== Minimum requirements ===
+
==== Minimum requirements ====
 
In order to use trace on the SiLabs SIM3L167 MCU devices, the following minimum requirements have to be met:
 
In order to use trace on the SiLabs SIM3L167 MCU devices, the following minimum requirements have to be met:
 
* J-Link software version V6.72b or later
 
* J-Link software version V6.72b or later
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* J-Link Plus V10 or later for TMC/ETB trace
 
* J-Link Plus V10 or later for TMC/ETB trace
   
  +
To rebuild the project our IDE Embedded Studio can be used. The recommended version to rebuild the projects is V6.30. But the examples are all prebuild and work out-of-the box with Ozone, so rebuilding is not necessary.
=== Specifics and limitations ===
 
  +
  +
==== Specifics and limitations ====
 
*For tracing, please make sure, that the resistors "R27 - R31" are removed from the evaluation board.
 
*For tracing, please make sure, that the resistors "R27 - R31" are removed from the evaluation board.
 
*The timing of the trace signal for this board is not Arm compliant, therefore the timing had to be adjusted in the Sample below.<br>For further information, please refer to the [https://www.segger.com/products/debug-probes/j-trace/technology/setting-up-trace/ setting up trace page on our website].
 
*The timing of the trace signal for this board is not Arm compliant, therefore the timing had to be adjusted in the Sample below.<br>For further information, please refer to the [https://www.segger.com/products/debug-probes/j-trace/technology/setting-up-trace/ setting up trace page on our website].
   
=== Streaming trace ===
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==== Streaming trace ====
 
The project has been tested with the minimum requirements mentioned above and a Silicon Labs ''SiM3L1xx 32-bit MCU LCD Development Kit''.
 
The project has been tested with the minimum requirements mentioned above and a Silicon Labs ''SiM3L1xx 32-bit MCU LCD Development Kit''.
   
 
'''Example project:''' [[Media:SiliconLabs_SIM3L167_Sample.zip | SiliconLabs_SIM3L167_Sample.zip]]
 
'''Example project:''' [[Media:SiliconLabs_SIM3L167_Sample.zip | SiliconLabs_SIM3L167_Sample.zip]]
   
=== Tested Hardware ===
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==== Tested Hardware ====
 
[[File:SiM3L1xx_32-bit_MCU_LCD_Development_Kit.jpg|none|thumb|SiM3L1xx 32-bit MCU LCD Development Kit]]
 
[[File:SiM3L1xx_32-bit_MCU_LCD_Development_Kit.jpg|none|thumb|SiM3L1xx 32-bit MCU LCD Development Kit]]
   
=== Reference trace signal quality ===
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==== Reference trace signal quality ====
 
The following pictures show oscilloscope measurements of trace signals output by the "Tested Hardware" using the example project.
 
The following pictures show oscilloscope measurements of trace signals output by the "Tested Hardware" using the example project.
 
All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes.
 
All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes.
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More information about correct trace timing can be found at the following [https://www.segger.com/products/debug-probes/j-trace/technology/setting-up-trace/ website].
 
More information about correct trace timing can be found at the following [https://www.segger.com/products/debug-probes/j-trace/technology/setting-up-trace/ website].
   
==== Trace clock signal quality ====
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===== Trace clock signal quality =====
 
The trace clock signal quality shows multiple trace clock cycles on the tested hardware as reference.
 
The trace clock signal quality shows multiple trace clock cycles on the tested hardware as reference.
 
[[File:SIM3L167_Multiple_TCLK.png|none|thumb|Trace clock signal quality]]
 
[[File:SIM3L167_Multiple_TCLK.png|none|thumb|Trace clock signal quality]]
   
==== Rise time ====
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===== Rise time =====
 
The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1.
 
The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1.
 
For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal.
 
For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal.
 
[[File:SIM3L167_Risetime_TCLK.png|none|thumb|TCLK rise time]]
 
[[File:SIM3L167_Risetime_TCLK.png|none|thumb|TCLK rise time]]
   
==== Setup time ====
+
===== Setup time =====
 
The setup time shows the relative setup time between a trace data signal and trace clock.
 
The setup time shows the relative setup time between a trace data signal and trace clock.
 
The measurement markers are set at 50% of the expected voltage level respectively.
 
The measurement markers are set at 50% of the expected voltage level respectively.

Latest revision as of 16:40, 15 June 2022

This article covers the Device specifics for the Silicon Labs (SiLabs) SIM3L-family device. It focuses on the use of J-Link/J-Trace with these devices.

Tracing on SIM3L-series devices

This section describes how to get started with trace on the Silicon Labs SIM3L MCUs. This section assumes that there is already a basic knowledge about trace in general (what is trace, what different implementations of trace are there, etc.). If this is not the case, we recommend to read Trace chapter in the J-Link User Manual (UM08001).

Note:

  • The sample projects come with a pre-configured project file for Ozone that runs out-of-the box.
  • The following sample project is designed to be used with J-Trace PRO for streaming trace, J-Link Plus for buffer tracing (TMC/ETB trace) and Ozone to demonstrate streaming trace.
  • In order to rebuild the sample project, SEGGER Embedded Studio can be used.
  • All examples are shipped with a compiled .JLinkScriptfile (.pex), should you need the original source, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/.

Tracing on SiLabs SIM3L167

Minimum requirements

In order to use trace on the SiLabs SIM3L167 MCU devices, the following minimum requirements have to be met:

  • J-Link software version V6.72b or later
  • Ozone V3.10j or later (if streaming trace and / or the sample project from below shall be used)
  • J-Trace PRO for Cortex-M HW version V1.0 or later for streaming trace
  • J-Link Plus V10 or later for TMC/ETB trace

To rebuild the project our IDE Embedded Studio can be used. The recommended version to rebuild the projects is V6.30. But the examples are all prebuild and work out-of-the box with Ozone, so rebuilding is not necessary.

Specifics and limitations

  • For tracing, please make sure, that the resistors "R27 - R31" are removed from the evaluation board.
  • The timing of the trace signal for this board is not Arm compliant, therefore the timing had to be adjusted in the Sample below.
    For further information, please refer to the setting up trace page on our website.

Streaming trace

The project has been tested with the minimum requirements mentioned above and a Silicon Labs SiM3L1xx 32-bit MCU LCD Development Kit.

Example project: SiliconLabs_SIM3L167_Sample.zip

Tested Hardware

SiM3L1xx 32-bit MCU LCD Development Kit

Reference trace signal quality

The following pictures show oscilloscope measurements of trace signals output by the "Tested Hardware" using the example project. All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes. If your trace signals look similar on your trace hardware, chances are good that tracing will work out-of-the-box using the example project. More information about correct trace timing can be found at the following website.

Trace clock signal quality

The trace clock signal quality shows multiple trace clock cycles on the tested hardware as reference.

Trace clock signal quality
Rise time

The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1. For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal.

TCLK rise time
Setup time

The setup time shows the relative setup time between a trace data signal and trace clock. The measurement markers are set at 50% of the expected voltage level respectively. The following picture shows such a measurement for the trace data signal 0 relative to the trace clock signal.

TD0 setup time