This article covers the Device specifics for the Silicon Labs (SiLabs) SIM3L-family device. It focuses on the use of J-Link/J-Trace with these devices.
Tracing on SIM3L-series devices
This section describes how to get started with trace on the Silicon Labs SIM3L MCUs. This section assumes that there is already a basic knowledge about trace in general (what is trace, what different implementations of trace are there, etc.). If this is not the case, we recommend to read Trace chapter in the J-Link User Manual (UM08001).
- The sample projects come with a pre-configured project file for Ozone that runs out-of-the box.
- The following sample project is designed to be used with J-Trace PRO for streaming trace, J-Link Plus for buffer tracing (TMC/ETB trace) and Ozone to demonstrate streaming trace.
- In order to rebuild the sample project, SEGGER Embedded Studio can be used.
- All examples are shipped with a compiled .JLinkScriptfile (.pex), should you need the original source it can be requested at email@example.com.
Tracing on SiLabs SIM3L167
In order to use trace on the SiLabs SIM3L167 MCU devices, the following minimum requirements have to be met:
- J-Link software version V6.72b or later
- Ozone V3.10j or later (if streaming trace and / or the sample project from below shall be used)
- J-Trace PRO for Cortex-M HW version V1.0 or later for streaming trace
- J-Link Plus V10 or later for TMC/ETB trace
The project has been tested with the minimum requirements mentioned above and a Silicon Labs SiM3L1xx 32-bit MCU LCD Development Kit.
Example project: SiliconLabs_SIM3L167_Sample.zip
Reference trace signal quality
The following pictures show oscilloscope measurements of trace signals output by the "Tested Hardware" using the example project. All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes. If your trace signals look similar on your trace hardware, chances are good that tracing will work out-of-the-box using the example project. More information about correct trace timing can be found at the following website.
Trace clock signal quality
The trace clock signal quality shows multiple trace clock cycles on the tested hardware as reference.
The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1. For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal.
The setup time shows the relative setup time between a trace data signal and trace clock. The measurement markers are set at 50% of the expected voltage level respectively. The following picture shows such a measurement for the trace data signal 0 relative to the trace clock signal.