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Revision as of 11:19, 9 December 2021 by Sebastian (talk | contribs) (Debugging)
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The SR6P7G7C7 is built on ARM® architecture technology and integrates innovations that are important for today’s and tomorrow’s automotive applications. SR6P7G7C7 integration MCUs have been designed to meet the requirements of domain controllers and ECUs with high integration requested in the architectures of connected update-able automated and electrified cars.

General information


By default only Cluster0_Core0 (Cortex-R52) is running. To enable all other Cortex-R52 cores establish a debug connection to Cluster0_Core0 (Cortex-R52) as during the connection procedure all other Cortex-R52 get enabled.

Flash programming

Flash programming of all below listed flash regions is done through Cluster0_Core0 (Cortex-R52). All other Cortex-R52 cores only allow debugging.

On-Chip Memory Regions

The internal flash is divided into 13 different regions:

Instance Name Size (bytes) Memory region
RWW partition 0 1792 KBytes 0x28000000 - 0x281BFFFF
RWW partition 1 2048 KBytes 0x281C0000 - 0x283BFFFF
RWW partition 2 1792 KBytes 0x28400000 - 0x285BFFFF
RWW partition 3 2048 KBytes 0x285C0000 - 0x287BFFFF
RWW partition 4 2048 KBytes 0x28800000 - 0x289FFFFF
RWW partition 5 2048 KBytes 0x28A00000 - 0x28BFFFFF
RWW partition 6 2048 KBytes 0x28C00000 - 0x28DFFFFF
RWW partition 7 2048 KBytes 0x28E00000 - 0x28FFFFFF
RWW partition 8 2048 KBytes 0x29000000 - 0x291FFFFF
RWW partition 9 2048 KBytes 0x29400000 - 0x295FFFFF
EEPROM 512 KBytes 0x29E00000 - 0x29E7FFFF
UTEST 32 KBytes 0x29F80000 - 0x283BFFFF
Boot Code Sector 16 KBytes 0x29FB8000 - 0x29FBBFFF

Evaluation Boards

  • ST SR6-EVB001 Rev. A evaluation board.

Example Application