Difference between revisions of "ST STM32F2"
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| + | This article describes device specifics of the ST STM32F2 series devices. |
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| + | The STM32F2 devices are Cortex-M3 based MCUs with low-power functionality. |
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__TOC__ |
__TOC__ |
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| + | == Internal Flash == |
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| − | This article describes device specifics of the ST STM32F2 series devices. |
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| + | The following flash regions are supported by J-Link. |
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| − | == Debugging with software watchdog enabled == |
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| + | {| class="seggertable" |
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| − | If the device shall be debugged with one of the software watchdogs (independed watchdog / window watchdog) enabled, there is an additional init step necessary to make the watchdog counter stop when the CPU is halted by the debugger. This is configured in the DBGMCU_CR register. The following sequence can be used to enable debugging with software watchdogs enabled: |
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| + | |- |
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| − | // |
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| + | ! Device !! Range !! Total size |
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| − | // Configure both watchdog timers to be halted if the CPU is halted by the debugger |
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| + | |- |
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| − | // |
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| + | | STM32F2xxxB || 0x0800_0000 - 0x0801_FFFF || 128 KB |
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| − | *((volatile int *)(0xE0042004)) |= (1 << 8) | (1 << 9); |
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| + | |- |
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| + | | STM32F2xxxC || 0x0800_0000 - 0x0803_FFFF || 256 KB |
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| + | |- |
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| + | | STM32F2xxxE || 0x0800_0000 - 0x0807_FFFF || 512 KB |
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| + | |- |
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| + | | STM32F2xxxF || 0x0800_0000 - 0x080B_FFFF || 768 KB |
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| + | |- |
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| + | | STM32F2xxxG || 0x0800_0000 - 0x080F_FFFF || 512 KB |
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| + | |- |
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| + | | All (opt. bytes) || 0x1FFF_C000 - 0x1FFF_C00F || 16 bytes |
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| + | |} |
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| + | |||
| + | == Reset == |
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| + | For the STM32F2 devices, the [[J-Link_Reset_Strategies#Type_0:_Normal | Cortex-M default reset strategy]] is used. |
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| + | |||
| + | == Debug specific == |
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| + | * If no connection can be established the J-Link will try to connect to the device via a connect under reset. |
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| + | * On connect, some DBGMCU registers will be written to |
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| + | ** freeze the watchdogs during halt to prevent unintended resets while debugging. |
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| + | ** prevent the debug connection from breaking after the CPU enters deepsleep. |
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| + | * When closing the J-Link connection, the DBGMCU registers are reset. |
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| + | |||
| + | == Securing/unsecuring the device == |
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| + | Please refer to [[STM32#MCU_Security | the related article here]]. |
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Revision as of 12:14, 21 November 2022
This article describes device specifics of the ST STM32F2 series devices. The STM32F2 devices are Cortex-M3 based MCUs with low-power functionality.
Internal Flash
The following flash regions are supported by J-Link.
| Device | Range | Total size |
|---|---|---|
| STM32F2xxxB | 0x0800_0000 - 0x0801_FFFF | 128 KB |
| STM32F2xxxC | 0x0800_0000 - 0x0803_FFFF | 256 KB |
| STM32F2xxxE | 0x0800_0000 - 0x0807_FFFF | 512 KB |
| STM32F2xxxF | 0x0800_0000 - 0x080B_FFFF | 768 KB |
| STM32F2xxxG | 0x0800_0000 - 0x080F_FFFF | 512 KB |
| All (opt. bytes) | 0x1FFF_C000 - 0x1FFF_C00F | 16 bytes |
Reset
For the STM32F2 devices, the Cortex-M default reset strategy is used.
Debug specific
- If no connection can be established the J-Link will try to connect to the device via a connect under reset.
- On connect, some DBGMCU registers will be written to
- freeze the watchdogs during halt to prevent unintended resets while debugging.
- prevent the debug connection from breaking after the CPU enters deepsleep.
- When closing the J-Link connection, the DBGMCU registers are reset.
Securing/unsecuring the device
Please refer to the related article here.
