Difference between revisions of "ST STM32F4"

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(NOTES:)
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//
 
//
 
*((volatile int *)(0xE0042008)) |= (1 << 11) | (1 << 12);
 
*((volatile int *)(0xE0042008)) |= (1 << 11) | (1 << 12);
  +
  +
== RTT ==
  +
  +
SEGGER's [[RTT]] can be used with a J-Link connected to a STM32F4 target device.<br>
  +
  +
=== Sample project ===
  +
For a sample [[Embedded Studio]] project, refer to the following .zip archive:<br>
  +
  +
[[Media:ST_STM32F446ZE_NUCLEO_RTT.zip | ST_STM32F446ZE_NUCLEO_RTT.zip ]]
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'''Note''': The above project was tested with the following setup:
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  +
{|
  +
| Target device || STM32F446ZE
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|-
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| Evalboard || NUCLEO-F446ZE (ST)
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|-
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| J-Link software version || V6.51b
  +
|-
  +
| Embedded Studio version || V4.18
  +
|}
  +
  +
=== Tested Hardware ===
  +
[[File:NUCLEO-F446ZE.png|none|thumb|NUCLEO-F446ZE Rev. B]]

Revision as of 09:30, 30 September 2019

Option byte programming

The STM32F4 series devices provide some option bytes which allow some "permanent" configuration as well as readout protection for the device. Unfortunately, the option bytes become effective immediately when programmed. This means when enabling the read protection of the device via option bytes, the programmer will immediately lose the access to the flash, without any possibility to verify the complete flash operation. Therefore, the option bytes cannot be programmed as part of the flash image. The sequence, to program the option bytes consists of multiple read / write accesses to special function registers of the STM32F4 MCU.

Via J-Flash / Flasher ARM

The sequence to program the option bytes, needs to be added to the exit-steps of the J-Flash project. The exit steps will be executed at the end of an successful auto-programming process (Target -> Auto). J-Flash comes with an example project for the STM32F405OE which contains the option byte programming sequence (File:STM32F405OE OptBytes.jflash). This sequence applies for all STM32F2 / F4 devices since they are compatible regarding option byte programming and can be adapted to fit custom requirements. The option byte values are transmitted in exit step # 5, which writes the OPTCR.

Wiki-STM32F4 OptionByteProg.png

Modification example (seting WDG_SW byte and read protection bit)

As mentioned above, the option bytes can be customized by changing step # 5 of the Exit steps above.

Necessary changes of "Step 5" in "Data" section:

Value Effect
0x0FFFAABC Read protection level 0, WDG_SW set to Hardware independent watchdog
0x0FFFAAEC Read protection level 0, WDG_SW set to Software independent watchdog
0x0FFFBBBC Read protection level 1, WDG_SW set to Hardware independent watchdog
0x0FFFBBEC Read protection level 1, WDG_SW set to Software independent watchdog
0x0FFFCCBC Read protection level 2, WDG_SW set to Hardware independent watchdog
0x0FFFCCEC Read protection level 2, WDG_SW set to Software independent watchdog

NOTES:

  1. For STM32F42xxx and STM32F43xxx devices, bit 4 is used for setting the single or dual bank flash memory option. In this example the default case (single bank flash memory) was selected.
  1. After changing WDG_SW, the device must be reset for the changes to take effect.

STM32F446xx (Q)SPI support

The ST STM32F446xx device series comes with a QUADSPI controller which allows memory mapped read accesses to any (Q)SPI flash, connected to the Quad-SPI interface of the MCU. This allows the J-Link DLL to support flash programming through the Quad-SPI interface. Unfortunately, there is no generic way how to implement flash programming because the used pins to connect the SPI flash is not defined but different pins can be used for the same QUADSPI alternate function and therefore, for each configuration, a slightly different RAMCode (different pin initialization / flash size) is required. We have developed a flash algorithm, which allows to program any common (Q)SPI flash, connected to the Quad-SPI interface of the ST STM32F446 device. The flash algorithm is based on the Open Flash Loader concept so it can easily exchanged if a pin configuration, different from the one used in the example flash algorithm, is required. In such cases, please get in touch with SEGGER directly (support@segger.com).

Example implementation

As described above, the reference flash algorithm is based on the Open Flash Loader and therefore needs to be added manually using a JLinkDevices.xml file. An example JLinkDevices.xml entry as well as the used pinout in the example flash algorithm is given below. This example assumes a Winbond W25Q16DV (2MB flash) connected to the Quad-SPI interface of the STM32F446xx. For further information regarding the Open Flash Loader and how to use the JLinkDevices.xml file, please refer to the J-Link User Manual (UM08001), chapter 10 Open Flash Loader.

Quad-SPI interface pins

The example algorithm uses the following port pins to interface the (Q)SPI flash.

Alternate function Port / Pin
QUADSPI_BK1_IO0 PF8
QUADSPI_BK1_IO1 PF9
QUADSPI_BK1_IO2 PE2
QUADSPI_BK1_IO3 PF6
QUADSPI_CLK PB2
QUADSPI_BK1_NCS PG6

JLinkDevices.xml

<Database>
  <Device>
    <ChipInfo Vendor="ST" Name="STM32F446ZE" WorkRAMAddr="0x20000000" WorkRAMSize="0x18000" Core="JLINK_CORE_CORTEX_M4" />
    <FlashBankInfo Name="Internal Flash" BaseAddr="0x90000000" MaxSize="0x200000" Loader="ST_STM32F446_Reference.elf" LoaderType="FLASH_ALGO_TYPE_OPEN" />
  </Device>
</Database>

Flash algorithm (*.elf)

This file contains the program routines used by the J-Link DLL during flash programming.

IAR example project

The example project contains a simple counter loop which is linked into the (Q)SPI flash memory region @ address 0x90000000. The project includes the JLinkDevices.xml file as well as the ST_STM32F446_Reference.elf. It runs out-of-the-box. Please note, that IAR EWARM must at least use the J-Link DLL version V6.01a, which supports the Open Flash Loader.

STM32F469xx (Q)SPI support

The ST STM32F469xx device series comes with a QUADSPI controller which allows memory mapped read accesses to any (Q)SPI flash, connected to the Quad-SPI interface of the MCU. This allows the J-Link DLL to support flash programming through the Quad-SPI interface. Unfortunately, there is no generic way how to implement flash programming because the used pins to connect the SPI flash is not defined but different pins can be used for the same QUADSPI alternate function and therefore, for each configuration, a slightly different RAMCode (different pin initialization / flash size) is required. We have developed a flash algorithm, which allows to program any common (Q)SPI flash, connected to the Quad-SPI interface of the ST STM32F469 device. The flash algorithm is based on the Open Flash Loader concept so it can easily exchanged if a pin configuration, different from the one used in the example flash algorithm, is required. In such cases, please get in touch with SEGGER directly (support@segger.com).

Example implementation

As described above, the reference flash algorithm is based on the Open Flash Loader and therefore needs to be added manually using a JLinkDevices.xml file. An example JLinkDevices.xml entry as well as the used pinout in the example flash algorithm is given below. This example assumes a Winbond W25Q16DV (2MB flash) connected to the Quad-SPI interface of the STM32F469xx. For further information regarding the Open Flash Loader and how to use the JLinkDevices.xml file, please refer to the J-Link User Manual (UM08001), chapter 10 Open Flash Loader.

Quad-SPI interface pins

The example algorithm uses the following port pins (as used on the STM32F469I-DISCO board) to interface the (Q)SPI flash.

Alternate function Port / Pin
QUADSPI_BK1_IO0 PF8
QUADSPI_BK1_IO1 PF9
QUADSPI_BK1_IO2 PF7
QUADSPI_BK1_IO3 PF6
QUADSPI_CLK PF10
QUADSPI_BK1_NCS PB6

JLinkDevices.xml

<Database>
  <Device>
   <ChipInfo Vendor="ST" Name="STM32F469NI" Core="JLINK_CORE_CORTEX_M4" />
   <FlashBankInfo Name="QSPI Flash" BaseAddr="0x90000000" MaxSize="0x01000000" Loader="ST_STM32F469I_Disco_QSPI.elf" LoaderType="FLASH_ALGO_TYPE_OPEN" />
  </Device>
</Database>

Flash algorithm (*.elf)

This file contains the program routines used by the J-Link DLL during flash programming.

IAR example project

The example project contains a simple counter loop which is linked into the (Q)SPI flash memory region @ address 0x90000000. The project includes the JLinkDevices.xml file as well as the ST_STM32F469I_Disco_QSPI.elf. It runs out-of-the-box. Please note, that IAR EWARM must at least use the J-Link DLL version V6.01a, which supports the Open Flash Loader.

Debugging with software watchdog enabled

If the device shall be debugged with one of the software watchdogs (independed watchdog / window watchdog) enabled, there is an additional init step necessary to make the watchdog counter stop when the CPU is halted by the debugger. This is configured in the DBGMCU_APB1_FZ register. The following sequence can be used to enable debugging with software watchdogs enabled:

//
// Configure both watchdog timers to be halted if the CPU is halted by the debugger
//
*((volatile int *)(0xE0042008)) |= (1 << 11) | (1 << 12);

RTT

SEGGER's RTT can be used with a J-Link connected to a STM32F4 target device.

Sample project

For a sample Embedded Studio project, refer to the following .zip archive:

ST_STM32F446ZE_NUCLEO_RTT.zip

Note: The above project was tested with the following setup:

Target device STM32F446ZE
Evalboard NUCLEO-F446ZE (ST)
J-Link software version V6.51b
Embedded Studio version V4.18

Tested Hardware

NUCLEO-F446ZE Rev. B