ST STM32F7

This article describes device specifics of the ST STM32F7 series devices. The STM32F7 devices are Cortex-M7 based MCUs with low-power functionality.

Flash

The following flash regions are supported by J-Link.

Device	Range	Total size
STM32F7xxx8	0x0800_0000 - 0x0800_FFFF	64 KB
STM32F7xxxC	0x0800_0000 - 0x0803_FFFF	256 KB
STM32F7xxxE	0x0800_0000 - 0x0807_FFFF	512 KB
STM32F7xxxG	0x0800_0000 - 0x080F_FFFF	1024 KB
STM32F7xxxI	0x0800_0000 - 0x081F_FFFF	2048 KB
All (opt. bytes)	0x1FFF_0000 - 0x1FFF_001F	32 bytes
All (QSPI)	0x9000_0000 - 0x93FF_FFFF (max)	64 MB (max)

Reset

For the STM32F0 devices, the Cortex-M default reset strategy is used.

Debug specific

• If no connection can be established the J-Link will try to connect to the device via a connect under reset.
• On connect, some DBGMCU registers will be written to
  • freeze the watchdogs during halt to prevent unintended resets while debugging.
  • prevent the debug connection from breaking after the CPU enters deepsleep.
• When closing the J-Link connection, the DBGMCU registers are reset.

QSPI support

The ST STM32F7xxx device series comes with a QUADSPI controller which allows memory mapped read accesses to any (Q)SPI flash, connected to the Quad-SPI interface of the MCU. This allows the J-Link DLL to support flash programming through the Quad-SPI interface. Unfortunately, there is no generic way how to implement flash programming because the pins used to connect the SPI flash are not defined. Different pins can be used for the same QUADSPI alternate function and therefore, for each configuration, a slightly different RAMCode (different pin initialization / flash size) is required. Our flash algorithms are based on the pin configurations used on the official evaluation boards. For pin configuration, different from the one used in the example flash algorithm, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/.

For further information regarding this as well as the flash algorithm, please refer to the following pages:

• STM32F72xx / STM32F73xx: STM32F723E Discovery
• STM32F74xx / STM32F75xx: STM32F746G Discovery
• STM32F76xx / STM32F77xx:
  • STM32F769I Discovery
  • STM32F769I EVAL

Supported pin configurations

J-Link supports multiple pin configurations for STM32F7 devices. There are several options to select a different loader than the default one.

Pin configuration/loader name	Notes
CLK@PB2_nCS@PB6_D0@PC9_D1@PC10_D2@PE2_D3@PD13	Default loader
CLK@PB2_nCS@PB6_D0@PD11_D1@PD12_D2@PE2_D3@PD13

Flash Dual Bank Mode

The ST STM32F7 series devices come with a dual-bank flash memory. The layout of the dual-bank flash memory can be configured by the user through the option byte nDBANK. By default, the value of this option byte is nDBANK == 1, which means that the flash is configured as single bank memory, while nDBANK == 0 means that the flash is configured as dual bank memory flash. The total flash size is exactly the same for both modes.

Problem description

• The sector layout is different depending on the nDBANK bit
• The flash algorithm has to behave different (pass different sector indices to erase sector)

By default, the J-Link flash loader assumes that the flash controller is configured for the single bank flash layout (nDBANK == 1) because it is the default configuration. In case of the flash controller is configured for the dual bank flash layout (nDBANK == 0), the default flash algorithm / sector layout won't work.

Solution

When operating the flash in dual bank flash mode (nDBANK == 0), the flash algorithm as well as the sector layout used by the J-Link DLL needs to be overwritten. This can be done using the SEGGER Flashloader. Please find below two precompiled flash algorithms, one for the 1MB and one for the 2MB variant of the STM32F7 device series. The algorithms assume that the flash is configured in dual bank mode. Detailed information how to use the precompiled flashloaders can be found in this article.

Dual Bank enabled (1 MB device)

• File:ST STM32F7xxxx DualBank 512KB Bank0.elf
• File:ST STM32F7xxxx DualBank 512KB Bank1.elf

 <Device>
 <!-- This entry will overwrite the existing device entry in the J-Link software, so that a custom flash algorithm is used for the internal flash -->
   <ChipInfo Vendor="ST" Name="STM32F767ZI" Core="JLINK_CORE_CORTEX_M7" />
   <FlashBankInfo Name="Flash Bank0" BaseAddr="0x08000000" MaxSize="0x00080000 " Loader="ST_STM32F7xxxx_1MB_DualBank_Bank0.elf" LoaderType="FLASH_ALGO_TYPE_OPEN" />
   <FlashBankInfo Name="Flash Bank1" BaseAddr="0x08080000" MaxSize="0x00080000 " Loader="ST_STM32F7xxxx_1MB_DualBank_Bank1.elf" LoaderType="FLASH_ALGO_TYPE_OPEN" />
 </Device>

Dual Bank enabled (2 MB device)

• File:ST STM32F7xxxx DualBank 2MB.elf

 <Device>
 <!-- This entry will overwrite the existing device entry in the J-Link software, so that a custom flash algorithm is used for the internal flash -->
   <ChipInfo Vendor="ST" Name="STM32F767ZI" Core="JLINK_CORE_CORTEX_M7" />
   <FlashBankInfo Name="Flash Bank" BaseAddr="0x08000000" MaxSize="0x00200000 " Loader="ST_STM32F7xxxx_DualBank_2MB.elf" LoaderType="FLASH_ALGO_TYPE_OPEN" />
 </Device>

Option byte programming

ST STM32F7 family has an integrated option byte flash, that allows the user to set certain options depending on the application requirements. For more details please refer to the corresponding manual from ST. The flash can be memory mapped accessed / programmed as usual flash memory.

Note:

When programming the option bytes, the following conditions must be met:

• Per bank: All option bytes must be written in one go. It is not possible to only write - for example - one word.
• Reserved bits must be written with "1" otherwise writing the option bytes will not work as expected and the verify of the written area will fail.