ST STM32F7

From SEGGER Wiki
Revision as of 17:08, 4 November 2020 by Erik (talk | contribs) (STM32F723xx / STM32F730xx QSPI support)
Jump to: navigation, search

QSPI support

The ST STM32F746xx device series comes with a QUADSPI controller which allows memory mapped read accesses to any (Q)SPI flash, connected to the Quad-SPI interface of the MCU. This allows the J-Link DLL to support flash programming through the Quad-SPI interface. Unfortunately, there is no generic way how to implement flash programming because the pins used to connect the SPI flash are not defined. Different pins can be used for the same QUADSPI alternate function and therefore, for each configuration, a slightly different RAMCode (different pin initialization / flash size) is required. We have developed a flash algorithm based on the ST STM32F746-DISCO evaluation board. This flash algorithm can be used to to program any common (Q)SPI flash, connected to the Quad-SPI interface of the ST STM32F746 device. The flash algorithm is based on the SEGGER Open Flashloader concept so it can easily be exchanged if a pin configuration, different from the one used in the example flash algorithm, is required. In such cases, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/.

For further information regarding this as well as the flash algorithm, please refer to the following pages:

Flash Dual Bank Mode

The ST STM32F7 series devices come with a dual-bank flash memory. The layout of the dual-bank flash memory can be configured by the user through the option byte nDBANK. By default, the value of this option byte is nDBANK == 1, which means that the flash is configured as single bank memory, while nDBANK == 0 means that the flash is configured as dual bank memory flash. The total flash size is exactly the same for both modes.

Problem description

  • The sector layout is different depending on the nDBANK bit
  • The flash algorithm has to behave different (pass different sector indices to erase sector)

By default, the J-Link flash loader assumes that the flash controller is configured for the single bank flash layout (nDBANK == 1) because it is the default configuration. In case of the flash controller is configured for the dual bank flash layout (nDBANK == 0), the default flash algorithm / sector layout won't work.

Solution

When operating the flash in dual bank flash mode (nDBANK == 0), the flash algorithm as well as the sector layout used by the J-Link DLL needs to be overwritten. This can be done using the SEGGER Open Flashloader. Please find below two precompiled flash algorithms, one for the 1MB and one for the 2MB variant of the STM32F7 device series. The algorithms assume that the flash is configured in dual bank mode. Detailed information how to use the precompiled flashloaders can be found here: https://wiki.segger.com/Adding_Support_for_New_Devices#Using_a_Precompiled_Flashloader

Option byte programming

ST STM32F7 family has an integrated option byte flash, that allows the user to set certain options depending on the application requirements. For more details please refer to the corresponding manual from ST.

STM32F76x and STM32F77x

Support has been added in V6.73a. The flash can be memory mapped accessed / programmed as usual flash memory. When programming the option bytes, the following conditions must be met:

  • Per bank: All option bytes must be written in one go. It is not possible to only write - for example - one word.
  • Reserved bits must be written with "1" otherwise writing the option bytes will not work as expected and the verify of the written area will fail.

STM32F72x/STM32F73x/STM32F74x/STM32F75x

Currently not supported. If support is needed, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/.