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STM32G4 option byte programming

For STM32G4 devices, the option byte page(s) can be programmed via J-Flash. When programming the option bytes, the following conditions must be met:

  • Per bank: All option bytes must be written in one go. It is not possible to only write - for example - one word.
  • Reserved bits must be written with "1" otherwise writing the option bytes will not work as expected and the verify of the written area will fail.

STM32G47xx Flash Dual Bank Mode

The ST STM32G47xx series devices come with a dual-bank flash memory. The layout of the dual-bank flash memory can be configured by the user through the option byte nDBANK. By default, the value of this option byte is DBANK == 1, which means that the flash is configured as dual bank memory while DBANK == 0 means that the flash is configured as single bank memory flash. The total flash size is exactly the same for both modes.

Problem description

  • The sector layout is different depending on the DBANK bit
  • The flash algorithm has to behave different (pass different sector indices to erase sector)

By default, the J-Link flash loader assumes that the flash controller is configured for the dual bank flash layout (DBANK == 1) because it is the default configuration. In case of the flash controller is configured for the single bank flash layout (DBANK == 0), the default flash algorithm / sector layout won't work.


When operating the flash in single bank flash mode (DBANK == 0), the flash algorithm as well as the sector layout used by the J-Link DLL needs to be overwritten. This can be done using the SEGGER Open Flashloader. Please find below three precompiled flash algorithms, one for the 128KB, one for the 256KB and one for the 512KB variant of the STM32G47xx device series. The algorithms assume that the flash is configured in single bank mode. Detailed information how to use the precompiled flashloaders can be found here:

Regarding the JLinkDevices.xml entry: Please use a new device name (e.g. "STM32G47xx_SingleBank") and don't reuse the original STM32G47xx MCU name within JLinkDevices.xml as this can lead to memory overlap issues. This is because only the first bank gets replaced with the new openflashloader entry and the second bank of the dual flash bank config remains.

Tracing on STM32G4 series

This section describes how to get started with trace on the ST STM32G4 MCUs. This section assumes that there is already a basic knowledge about trace in general (what is trace, what different implementations of trace are there, etc.). If this is not the case, we recommend to read Trace chapter in the J-Link User Manual (UM08001).


  • The sample projects come with a pre-configured project file for Ozone that runs out-of-the box.
  • The following sample project is designed to be used with J-Trace PRO for streaming trace and Ozone to demonstrate streaming trace.
  • In order to rebuild the sample project, SEGGER Embedded Studio can be used.
  • All examples are shipped with a compiled .JLinkScriptfile (.pex), should you need the original source it can be requested at

Tracing on ST STM32G484

Minimum requirements

In order to use trace on the ST STM32G484 MCU devices, the following minimum requirements have to be met:

  • J-Link software version V6.80a or later
  • Ozone V3.20 or later (if streaming trace and / or the sample project from below shall be used)
  • J-Trace PRO for Cortex-M HW version V1.0 or later for streaming trace

Streaming trace

The project has been tested with the minimum requirements mentioned above and a STM32G474-EVAL board.

Example project:


The eval board used for this example setup needs some hardware modifications for trace to work reliably as the trace pins are shared with multiple peripherals that would otherwise impact the signal quality. For more information consult the boards user manual. Please note that these modifications will also disable the JTAG interface so only SWD can be used on this particular board in parallel with pin tracing.

Tested Hardware


Reference trace signal quality

The following pictures show oscilloscope measurements of trace signals output by the "Tested Hardware" using the example project. All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes. If your trace signals look similar on your trace hardware, chances are good that tracing will work out-of-the-box using the example project. More information about correct trace timing can be found at the following website.

Trace clock signal quality

The trace clock signal quality shows multiple trace clock cycles on the tested hardware as reference.

Trace clock signal quality
Rise time

The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1. For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal.

TCLK rise time
Setup time

The setup time shows the relative setup time between a trace data signal and trace clock. The measurement markers are set at 50% of the expected voltage level respectively. The following picture shows such a measurement for the trace data signal 0 relative to the trace clock signal.

TD0 setup time