Difference between revisions of "ST STM32MP1"

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(Default QSPI Pin mapping)
(Default QSPI Pin mapping)
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'''WARNING:'''
 
'''WARNING:'''
The QSPI programming in this device is done through AP[2] - Cortex-M4. In order to allow J-Link to communicate with the Cortex-M4 AP the STM32MP1xx needs to be set in "Engineering Boot Mode".
+
The QSPI programming in this device is done through AP[2] - Cortex-M4. In order to allow J-Link to communicate with the Cortex-M4 AP the STM32MP1xx needs to be set in '''"Engineering Boot Mode"'''.
 
 
 
'''NOTE:'''
 
'''NOTE:'''

Revision as of 16:14, 11 September 2019

Overview

The STM32MP15x is a heterogeneous dual-core MCU with a Cortex-M4 and one or two Cortex-A7 cores.

Supported QSPI modes

Currently, J-Link supports Dual QSPI Flash-Mode and Single QSPI Flashbank(Bank 1 or Bank2) programming.

Default QSPI Pin mapping

Port Pin Pin Function Alt Func
GPIO_B 6 QSPI_BK1_NCS AF_10
GPIO_F 6 QSPI_BK1_IO3 AF_9
GPIO_F 7 QSPI_BK1_IO2 AF_9
GPIO_F 9 QSPI_BK1_IO1 AF_10
GPIO_F 8 QSPI_BK1_IO0 AF_10
GPIO_F 10 QSPI_CLK AF_9
GPIO_C 0 QSPI_BK2_NCS AF_10
GPIO_G 7 QSPI_BK2_IO3 AF_11
GPIO_G 10 QSPI_BK2_IO2 AF_10
GPIO_H 3 QSPI_BK2_IO1 AF_10
GPIO_H 2 QSPI_BK2_IO0 AF_10


WARNING: The QSPI programming in this device is done through AP[2] - Cortex-M4. In order to allow J-Link to communicate with the Cortex-M4 AP the STM32MP1xx needs to be set in "Engineering Boot Mode".

NOTE: If you wish to use a QSPI GPIO configuration different than the default provided one, please get in contact with SEGGER Support.