Difference between revisions of "ST STM32MP1"

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(Default QSPI Pin mapping)
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= Default QSPI Pin mapping =
 
= Default QSPI Pin mapping =
   
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{| class="wikitable"
{| style="border-spacing:0;width:9.49cm;"
 
 
|-
 
|-
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! Port !! Pin !! Pin Function !! Alt Func
| style="background-color:transparent;border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding:0.097cm;color:#000000;" | '''Port'''
 
| style="background-color:transparent;border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding:0.097cm;color:#000000;" | '''Pin'''
 
| style="background-color:transparent;border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding:0.097cm;color:#000000;" | '''Pin Function '''
 
| style="background-color:transparent;border:0.5pt solid #000000;padding:0.097cm;color:#000000;" | '''Alt Func'''
 
 
|-
 
|-
  +
| GPIO_B || 6 || QSPI_BK1_NCS || AF_10
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding:0.097cm;color:#000000;" | GPIO_B
 
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding:0.097cm;color:#000000;" | 6
 
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding:0.097cm;color:#000000;" | QSPI_BK1_NCS
 
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:0.5pt solid #000000;padding:0.097cm;color:#000000;" | AF_10
 
 
|-
 
|-
  +
| GPIO_F || 6 || QSPI_BK1_IO3 || AF_9
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding:0.097cm;color:#000000;" | GPIO_F
 
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding:0.097cm;color:#000000;" | 6
 
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding:0.097cm;color:#000000;" | QSPI_BK1_IO3
 
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:0.5pt solid #000000;padding:0.097cm;color:#000000;" | AF_9
 
 
|-
 
|-
  +
| GPIO_F || 7 || QSPI_BK1_IO2 || AF_9
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding:0.097cm;color:#000000;" | GPIO_F
 
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding:0.097cm;color:#000000;" | 7
 
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding:0.097cm;color:#000000;" | QSPI_BK1_IO2
 
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:0.5pt solid #000000;padding:0.097cm;color:#000000;" | AF_9
 
 
|-
 
|-
  +
| GPIO_F || 9 || QSPI_BK1_IO1 || AF_10
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding:0.097cm;color:#000000;" | GPIO_F
 
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding:0.097cm;color:#000000;" | 9
 
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding:0.097cm;color:#000000;" | QSPI_BK1_IO1
 
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:0.5pt solid #000000;padding:0.097cm;color:#000000;" | AF_10
 
 
|-
 
|-
  +
| GPIO_F || 8 || QSPI_BK1_IO0 || AF_10
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding:0.097cm;color:#000000;" | GPIO_F
 
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding:0.097cm;color:#000000;" | 8
 
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding:0.097cm;color:#000000;" | QSPI_BK1_IO0
 
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:0.5pt solid #000000;padding:0.097cm;color:#000000;" | AF_10
 
 
|-
 
|-
  +
| GPIO_F || 10 || QSPI_CLK || AF_9
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding:0.097cm;color:#000000;" | GPIO_F
 
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding:0.097cm;color:#000000;" | 10
 
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding:0.097cm;color:#000000;" | QSPI_CLK
 
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:0.5pt solid #000000;padding:0.097cm;color:#000000;" | AF_9
 
 
|-
 
|-
  +
| GPIO_C || 0 || QSPI_BK2_NCS || AF_10
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding:0.097cm;color:#000000;" | GPIO_C
 
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding:0.097cm;color:#000000;" | 0
 
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding:0.097cm;color:#000000;" | QSPI_BK2_NCS
 
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:0.5pt solid #000000;padding:0.097cm;color:#000000;" | AF_10
 
 
|-
 
|-
  +
| GPIO_G || 7 || QSPI_BK2_IO3 || AF_11
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding:0.097cm;color:#000000;" | GPIO_G
 
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding:0.097cm;color:#000000;" | 7
 
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding:0.097cm;color:#000000;" | QSPI_BK2_IO3
 
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:0.5pt solid #000000;padding:0.097cm;color:#000000;" | AF_11
 
 
|-
 
|-
  +
| GPIO_G || 10 || QSPI_BK2_IO2 || AF_10
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding:0.097cm;color:#000000;" | GPIO_G
 
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding:0.097cm;color:#000000;" | 10
 
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding:0.097cm;color:#000000;" | QSPI_BK2_IO2
 
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:0.5pt solid #000000;padding:0.097cm;color:#000000;" | AF_10
 
 
|-
 
|-
  +
| GPIO_H || 3 || QSPI_BK2_IO1 || AF_10
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding:0.097cm;color:#000000;" | GPIO_H
 
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding:0.097cm;color:#000000;" | 3
 
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding:0.097cm;color:#000000;" | QSPI_BK2_IO1
 
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:0.5pt solid #000000;padding:0.097cm;color:#000000;" | AF_10
 
 
|-
 
|-
  +
| GPIO_H || 2 || QSPI_BK2_IO0 || AF_10
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding:0.097cm;color:#000000;" | GPIO_H
 
  +
|}
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding:0.097cm;color:#000000;" | 2
 
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding:0.097cm;color:#000000;" | QSPI_BK2_IO0
 
| style="background-color:transparent;border-top:none;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:0.5pt solid #000000;padding:0.097cm;color:#000000;" | AF_10
 
|-
 
|}
 
 
 
   
 
'''WARNING:'''
 
'''WARNING:'''

Revision as of 17:54, 16 December 2019

Overview

The STM32MP15x is a heterogeneous dual-core MCU with a Cortex-M4 and one or two Cortex-A7 cores.

Supported QSPI modes

Currently, J-Link supports Dual QSPI Flash-Mode and Single QSPI Flashbank(Bank 1 or Bank2) programming.

Default QSPI Pin mapping

Port Pin Pin Function Alt Func
GPIO_B 6 QSPI_BK1_NCS AF_10
GPIO_F 6 QSPI_BK1_IO3 AF_9
GPIO_F 7 QSPI_BK1_IO2 AF_9
GPIO_F 9 QSPI_BK1_IO1 AF_10
GPIO_F 8 QSPI_BK1_IO0 AF_10
GPIO_F 10 QSPI_CLK AF_9
GPIO_C 0 QSPI_BK2_NCS AF_10
GPIO_G 7 QSPI_BK2_IO3 AF_11
GPIO_G 10 QSPI_BK2_IO2 AF_10
GPIO_H 3 QSPI_BK2_IO1 AF_10
GPIO_H 2 QSPI_BK2_IO0 AF_10

WARNING: The QSPI programming in this device is done through AP[2] - Cortex-M4. In order to allow J-Link to communicate with the Cortex-M4 AP the STM32MP1xx needs to be set in "Engineering Boot Mode".

NOTE: If you wish to use a QSPI GPIO configuration different than the default provided one, please get in contact with SEGGER Support.