ST STM32L4

From SEGGER Wiki
Revision as of 07:51, 30 March 2023 by Matthias (talk | contribs) (STM32L476xx (Q)SPI support)
Jump to: navigation, search

This article describes device specifics of the ST STM32L4 and STM32L4+ series devices. The STM32L4 devices are Cortex-M4 based low power MCUs.

Flash

The following flash regions are supported by J-Link.

Device Range Total size
Main flash memory
STM32L4xxx8 0x0800_0000 - 0x0800_FFFF 64 KB
STM32L4xxxB 0x0800_0000 - 0x0801_FFFF 128 KB
STM32L4xxxC 0x0800_0000 - 0x0803_FFFF 256 KB
STM32L4xxxE 0x0800_0000 - 0x0807_FFFF 512 KB
STM32L4xxxG 0x0800_0000 - 0x080F_FFFF 1024 KB
STM32L4xxxI 0x0800_0000 - 0x081F_FFFF 2048 KB
(Q)SPI flash[1]
STM32L4+ 0x9000_0000 - 0x903F_FFFF (max) 4 MB (max)

Determine dual-bank setting

To determine whether dual-bank is set or not, the corresponding bit in the Flash option register (FLASH_OPTR, 0x4002 2020) can be read:

  • For 1MB devices: DB1M (bit-pos 21)
  • For 2MB devices: DBANK (bit-pos 22)

The following lines can be used in the J-Link Commander to read FLASH_OPTR:

r
mem32 0x40022020 1

Dualbank Flash Programming

The ST STM32L4 series devices come with a dual-bank flash memory. The layout of the dual-bank flash memory can be configured by the user through the option byte DUALBANK. By default, the value of this option byte is DUALBANK == 1, which means that the flash is configured as dual bank memory while DUALBANK == 0 means that the flash is configured as single bank memory flash. In dual-bank mode, the flash boot source can be switched between bank 1 or bank 2. In single-bank mode, flash always boots from bank 1. The total flash size is exactly the same for both modes. Another advantage of using DUALBANK is that both banks can be accessed in parallel (e.g. reading bank 1 while programming bank 2).

Problem description

The flash algorithm has to behave differently, depending on the active flash bank mode configuration as the flash controller expects different page indices for the same destination address.

Solution

Since V7.86a J-Link comes out of the box with two different flash loaders: One for single bank and one for dual bank configuration. Please see the multiple loader article on how to select a different loader.

QSPI Support

STM32L476xx (Q)SPI support

The ST STM32L476xx device series comes with a QUADSPI controller which allows memory mapped read accesses to any (Q)SPI flash, connected to the Quad-SPI interface of the MCU. This allows the J-Link DLL to support flash programming through the Quad-SPI interface. Unfortunately, there is no generic way how to implement flash programming because the used pins to connect the SPI flash is not defined. Different pins can be used for the same QUADSPI alternate function and therefore, for each configuration, a slightly different RAMCode (different pin initialization / flash size) is required. We have developed two flash algorithms based on a different pin layout. One is based on the ST STM32L476-DISCO evaluation board, the other one is based on the ST STM32L476G Eval board. These flash algorithms can be used to to program any common (Q)SPI flash, connected to the Quad-SPI interface of the ST STM32L476 device. The flash algorithms are based on the SEGGER Open Flash Loader concept so they can easily be exchanged if a pin configuration, different from the one used in the example flash algorithms, is required. In such cases, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/.

For further information regarding this as well as the flash algorithms, please refer to the following pages:

STM32L496xx (Q)SPI support

For STM32L496xx QSPI support is implemented with similar context to STM32L476xx.

For further information regarding this as well as the flash algorithms, please refer to the following pages:

STM32L+ (Q)SPI support

The ST STM32L4Pxxx / STM32L4Qxxx / STM32L4Rxxx / STM32L4Sxxx device series comes with a OCTASPI controller which allows memory mapped read accesses to any (Q)SPI flash, connected to the Octa-SPI interface of the MCU. This allows the J-Link DLL to support flash programming through the Octa-SPI interface. Unfortunately, there is no generic way how to implement flash programming because the used pins to connect the SPI flash is not defined. Different pins can be used for the same OCTASPI alternate function and therefore, for each configuration, a slightly different RAMCode (different pin initialization / flash size) is required. We have developed one flash algorithm based on a pin layout of the ST STM32L4R9 DISCO evaluation board. This flash algorithm can be used to to program any common (Q)SPI flash, connected to the Octa-SPI interface of the ST STM32L4Rxxx / STM32L4Sxxx series device. The flash algorithms are based on the SEGGER Open Flash Loader concept so they can easily be exchanged if a pin configuration, different from the one used in the example flash algorithms, is required. In such cases, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/.

For further information regarding this as well as the flash algorithms, please refer to the following pages:

Reset

For the STM32L4 devices, the Cortex-M default reset strategy is used.

Debug specific

Please refer to the generic STM32 article.

Option byte programming

Direct option byte programming is not (yet) implemented for the ST STM32L4. However, the same method used to lock/unlock the devices can be used as described in Securing/unsecuring the device can be used to adjust any option bytes.

Securing/unsecuring the device

Please refer to the generic STM32 article.