Difference between revisions of "SiFive Arty FPGA Dev Kit"
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| − | This article describes |
+ | This article describes specifics for the SiFive Arty FPGA Dev Kit. |
| − | == SWO == |
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| − | Auto SWO speed calculation of J-Link does not work for the Silicon Labs EFM32 series devices. |
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| + | == Preparing for J-Link == |
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| − | *Normal SWO Speed calculation: <CPUFreq> / n |
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| + | The SiFive Arty FPGA Dev Kit does not come with a standard debug connector but populates the debug JTAG signals on a custom connector. Therefore, it needs to be manually wired in case J-Link shall be connected to it |
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| − | *EFM32 specific:Chip-internally wired to a fixed 14 MHz clock (AUXHFRCO) |
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| − | |||
| − | For utilities like J-Link SWOViewer or similar: |
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| − | *Select 14 MHz as CPU speed (no matter what the CPU is really running at) to make the normal calculation working |
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Revision as of 18:54, 1 September 2017
Contents
This article describes specifics for the SiFive Arty FPGA Dev Kit.
Preparing for J-Link
The SiFive Arty FPGA Dev Kit does not come with a standard debug connector but populates the debug JTAG signals on a custom connector. Therefore, it needs to be manually wired in case J-Link shall be connected to it
