Difference between revisions of "SiFive Arty FPGA Dev Kit"
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== Preparing for J-Link == |
== Preparing for J-Link == |
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The SiFive Arty FPGA Dev Kit does not come with a standard debug connector but populates the debug JTAG signals on a custom connector. Therefore, it needs to be manually wired in case J-Link shall be connected to it |
The SiFive Arty FPGA Dev Kit does not come with a standard debug connector but populates the debug JTAG signals on a custom connector. Therefore, it needs to be manually wired in case J-Link shall be connected to it |
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[[File:Wiki-sifive_arty_board.png]] |
[[File:Wiki-sifive_arty_board.png]] |
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Revision as of 18:57, 1 September 2017
Contents
This article describes specifics for the SiFive Arty FPGA Dev Kit.
Preparing for J-Link
The SiFive Arty FPGA Dev Kit does not come with a standard debug connector but populates the debug JTAG signals on a custom connector. Therefore, it needs to be manually wired in case J-Link shall be connected to it
