Difference between revisions of "SiFive Arty FPGA Dev Kit"
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In the following, it is described how the pins of connector JD on the ARTY board needs to be wired to J-Link. All pins of the J-Link side refer to the standard 0.1" 20-pin connector of J-Link. |
In the following, it is described how the pins of connector JD on the ARTY board needs to be wired to J-Link. All pins of the J-Link side refer to the standard 0.1" 20-pin connector of J-Link. |
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| + | |+Wiring connection |
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| + | ! Pin ARTY |
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| + | ! Pin J-Link |
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| + | ! Description |
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| + | |- |
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| + | |STM32F0 |
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| + | |Cortex-M0 |
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| + | |scope="col" style="text-align:center" | [[File:YES.png|20px|link=]] |
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| + | |- |
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| + | |} |
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[[File:Wiki-sifive_arty_board.png]] |
[[File:Wiki-sifive_arty_board.png]] |
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Revision as of 19:00, 1 September 2017
Contents
This article describes specifics for the SiFive Arty FPGA Dev Kit.
Preparing for J-Link
The SiFive Arty FPGA Dev Kit does not come with a standard debug connector but populates the debug JTAG signals on a custom connector. Therefore, it needs to be manually wired in case J-Link shall be connected to it.
In the following, it is described how the pins of connector JD on the ARTY board needs to be wired to J-Link. All pins of the J-Link side refer to the standard 0.1" 20-pin connector of J-Link.
| Pin ARTY | Pin J-Link | Description |
|---|---|---|
| STM32F0 | Cortex-M0 | 
|
