https://wiki.segger.com/index.php?title=SiFive_E24&feed=atom&action=historySiFive E24 - Revision history2024-03-28T12:53:02ZRevision history for this page on the wikiMediaWiki 1.31.16https://wiki.segger.com/index.php?title=SiFive_E24&diff=10068&oldid=prevAlex: Created page with "The SiFive E24 is a 32-bit (RV32) core of the SiFive E2 series cores, designed by SiFive. __TOC__ = Minimum required J-Link software version = The E24 and E24ARTY device sel..."2021-05-26T08:52:39Z<p>Created page with "The SiFive E24 is a 32-bit (RV32) core of the SiFive E2 series cores, designed by SiFive. __TOC__ = Minimum required J-Link software version = The E24 and E24ARTY device sel..."</p>
<p><b>New page</b></p><div>The SiFive E24 is a 32-bit (RV32) core of the SiFive E2 series cores, designed by SiFive.<br />
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= Minimum required J-Link software version =<br />
The E24 and E24ARTY device selection are supported since V7.22 of the [https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack J-Link software].<br />
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= E24ARTY device selection =<br />
The E24ARTY is a special device that can be selected for J-Link. It selects the standard SiFive E24 that is implemented for the sample bitstream as part of the [[SiFive E24 Standard Core Dev Kit]]. Device specifics include:<br />
* Memory map<br />
* Flash banks<br />
As the E24 is a customizable core, the E24ARTY selection may not be appropriate for customized cores but for the standard one running on the ARTY-100T FPGA evaluation board only.<br />
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= RTT support =<br />
As the core does not support System Bus Access (SBA), RTT is '''not supported for this core'''.<br />
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= HSS access =<br />
As the core does not support System Bus Access (SBA), HSS is '''not supported for this core'''.</div>Alex