Difference between revisions of "SiFive S54"
| Line 1: | Line 1: | ||
| − | The SiFive S54 is a 64-bit (RV64) core, designed by SiFive. |
+ | The SiFive S54 is a 64-bit (RV64) core of the SiFive S5 series cores, designed by SiFive. |
__TOC__ |
__TOC__ |
||
| Line 11: | Line 11: | ||
* Flash banks |
* Flash banks |
||
As the S54 is a customizable core, the S54ARTY selection may not be appropriate for customized cores but for the standard one running on the ARTY-100T FPGA evaluation board only. |
As the S54 is a customizable core, the S54ARTY selection may not be appropriate for customized cores but for the standard one running on the ARTY-100T FPGA evaluation board only. |
||
| + | |||
| + | = RTT support = |
||
| + | As the core supports System Bus Access (SBA), RTT is supported for this core. |
||
| + | |||
| + | = HSS access = |
||
| + | As the core supports System Bus Access (SBA), RTT is supported for this core. |
||
Latest revision as of 00:56, 25 May 2021
The SiFive S54 is a 64-bit (RV64) core of the SiFive S5 series cores, designed by SiFive.
Contents
Minimum required J-Link software version
The S54 and S54ARTY device selection are supported since V7.22 of the J-Link software.
S54ARTY device selection
The S54ARTY is a special device that can be selected for J-Link. It selects the standard SiFive S54 that is implemented for the sample bitstream as part of the SiFive S54 Standard Core Dev Kit. Device specifics include:
- Memory map
- Flash banks
As the S54 is a customizable core, the S54ARTY selection may not be appropriate for customized cores but for the standard one running on the ARTY-100T FPGA evaluation board only.
RTT support
As the core supports System Bus Access (SBA), RTT is supported for this core.
HSS access
As the core supports System Bus Access (SBA), RTT is supported for this core.
