Difference between revisions of "Synergy"

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(Created page with "== Using SWO on Synergy Devices == In general, the J-Link DLL expects the trace clock to be equal to the CPU clock. As the Synergy device series allows to enable a pre-scaler...")
 
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== Using SWO on Synergy Devices ==
 
== Using SWO on Synergy Devices ==
In general, the J-Link DLL expects the trace clock to be equal to the CPU clock. As the Synergy device series allows to enable a pre-scaler for trace clock, this assumption is no longer valid resulting in incorrect SWO data are read. To make sure that the J-Link DLL behaves as expected, please make sure to enter not the actual CPU clock but the CPU clock multiplied with the trace clock divider configured in the Trace Clock Control Regigster (TRCKCR).
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In general, the J-Link DLL expects the trace clock to be equal to the CPU clock. As the Synergy device series allows to enable a pre-scaler for trace clock, this assumption is no longer valid resulting in incorrect SWO data are read. To make sure that the J-Link DLL behaves as expected, please make sure to not enter the actual CPU clock but the CPU clock multiplied with the ICKdivider configured in the System Clock Division Control Register (SCKDIVCR) divided by the trace clock divider configured in the Trace Clock Control Regigster (TRCKCR).
   
 
Example (S3A7):
 
Example (S3A7):
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*Trace Clock Control Register (TRCKCR[TRCK[3:0]]): 0x1 --> /2
 
*Trace Clock Control Register (TRCKCR[TRCK[3:0]]): 0x1 --> /2
   
ICLK = 8MHz * 1 / 16 = 500Hz CPU clock
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ICLK = 8MHz * 1 / 16 = 500Hz CPU clock
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TRCLK = ICLK * 1 / 2 = 250Hz Trace / SWO clock
TRCLK =
 
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CPU clock to be entered in the IDE project = ICLK * ICKdivider / TRCKdivider = 500 Hz * 16 / 2 = 4 kHz

Revision as of 14:41, 8 February 2017

Using SWO on Synergy Devices

In general, the J-Link DLL expects the trace clock to be equal to the CPU clock. As the Synergy device series allows to enable a pre-scaler for trace clock, this assumption is no longer valid resulting in incorrect SWO data are read. To make sure that the J-Link DLL behaves as expected, please make sure to not enter the actual CPU clock but the CPU clock multiplied with the ICKdivider configured in the System Clock Division Control Register (SCKDIVCR) divided by the trace clock divider configured in the Trace Clock Control Regigster (TRCKCR).

Example (S3A7):

  • MOCO (8MHz)
  • System Clock Division Control Register (SCKDIVCR[ICK[2:0]]): 0x4 --> * 1 / 16
  • System Clock Source Control Register (SCKSCR[CKSEL[2:0]]): 0x1 --> MOCO selected as source for the ICLK (System Clock) and TRCLK (Trace Clock)
  • Trace Clock Control Register (TRCKCR[TRCK[3:0]]): 0x1 --> /2

ICLK = 8MHz * 1 / 16 = 500Hz CPU clock TRCLK = ICLK * 1 / 2 = 250Hz Trace / SWO clock

CPU clock to be entered in the IDE project = ICLK * ICKdivider / TRCKdivider = 500 Hz * 16 / 2 = 4 kHz