Synergy

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Using SWO on Synergy Devices

In general, the J-Link DLL expects the trace clock to be equal to the CPU clock. As the Synergy device series allows to enable a pre-scaler for trace clock, this assumption is no longer valid resulting in incorrect SWO data are read. To make sure that the J-Link DLL behaves as expected, please make sure to enter not the actual CPU clock but the CPU clock multiplied with the trace clock divider configured in the Trace Clock Control Regigster (TRCKCR).

Example (S3A7):

  • MOCO (8MHz)
  • System Clock Division Control Register (SCKDIVCR[ICK[2:0]]): 0x4 --> * 1 / 16
  • System Clock Source Control Register (SCKSCR[CKSEL[2:0]]): 0x1 --> MOCO selected as source for the ICLK (System Clock) and TRCLK (Trace Clock)
  • Trace Clock Control Register (TRCKCR[TRCK[3:0]]): 0x1 --> /2

ICLK = 8MHz * 1 / 16 = 500Hz CPU clock TRCLK =