Difference between revisions of "Syntacore SCR1"

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The Syntacore SCR1 is a 32-bit (RV32) core, designed by [https://syntacore.com/page/products/processor-ip/scr1 Syntacore].
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__TOC__
 
__TOC__
   
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= Requirements =
This article describes specifics for the SiFive Arty FPGA Dev Kit.
 
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* A current J-Link model with RISC-V support
 
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* [https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack J-Link software] V6.44d or later. Older J-Link software versions will not work.
== Preparing for J-Link ==
 
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* The SCR1 device selection is supported since V6.44d
Syntacore provides a reference FPGA bistream for the Digilent ARTY FPGA dev kit, which allows to implement a RISC-V core. The Digilent ARTY FPGA dev kit does not come with a standard debug connector but populates the debug JTAG signals on the JD connector of the eval board. Therefore, it needs to be manually wired in case J-Link shall be connected to it.
 
 
In the following, it is described how the pins of JD connector on the ARTY board needs to be wired to J-Link. All pins of the J-Link side refer to the standard 0.1" 20-pin connector of J-Link.
 
 
{| class="wikitable"
 
|+Wiring connection
 
! Pin ARTY
 
! Pin J-Link
 
! Description
 
|-
 
|1
 
|13
 
|TDO
 
|-
 
|2
 
|3
 
|nTRST
 
|-
 
|3
 
|9
 
|TCK
 
|-
 
|7
 
|5
 
|TDI
 
|-
 
|8
 
|7
 
|TMS
 
|-
 
|9
 
|15
 
|nRESET
 
|-
 
|11
 
|4
 
|GND
 
|-
 
|12
 
|1
 
|VTref
 
|}
 
 
'''Note:''' The pins on the JD connector are numbered as follows:
 
{| class="wikitable"
 
|-
 
|6
 
|5
 
|4
 
|3
 
|2
 
|1
 
|-
 
|12
 
|11
 
|10
 
|9
 
|8
 
|7
 
|}
 
 
<Photo>
 
 
== Debugging in FreedomStudio ==
 
 
'''Before continuing, make sure that you have J-Link software package V6.20c or later installed''': [https://www.segger.com/downloads/jlink/ Download J-Link software package]
 
 
In the following, the procedure how to setup a J-Link debug session in SiFive FreedomStudio is described.
 
This tutorial assumes that there is already a compiling project present in FreedomStudio.
 
   
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= RTT support =
If not, please find a selection of example projects [[#Example projects for FreedomStudio | here]].
 
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As the core does not support System Bus Access (SBA), RTT is '''not''' supported for this core.
   
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= HSS access =
* Click on the arrow right next to the debug bug<br>[[File:FreedomStudio_Debug.png]]
 
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As the core does not support System Bus Access (SBA), HSS is '''not''' supported for this core.
* Double click on "GDB SEGGER J-Link Debugging"<br>[[File:FreedomStudio_NewDebugConfig.png]]
 
* Double click the newly generated configuration
 
* Click on the "Debugger" tab and make sure the settings look like below (the ones with the red border are non-default ones)<br>[[File:FreedomStudio_Debug_Debugger.png]]
 
* Click on the "Startup" tab and make sure the settings look like below (the ones with the red border are non-default ones)<br>[[File:FreedomStudio_Debug_Startup.png]]
 
   
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= Limitations =
=== Set program counter at ===
 
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* When debugging on the Syntacore SCR1, the max. JTAG speed that can be used is 1/12 of the CPU speed, so usually fJTAG has to be <= 2 MHz. Speeds above this limit will result in unstable operation of the debug interface on the device. The device sometimes simply returns garbage status info and data on debug module accesses. '''This is not a limitation of J-Link but of the Syntacore SCR1'''
When debugging in QSPI, this option can be disabled. When debugging in RAM, it should point to the base address of region marked as executable (x) in the linker file. (Usually 0x80000000 for RAM projects)
 
   
== Example projects for FreedomStudio ==
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= Example projects =
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[[File:Syntacore_SCR1_Arty_ES.zip]]
In the following, sample projects for the ARTY board running the SiFive FE310 MCU FPGA stream, can be downloaded.
 
   
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Requires [https://www.segger.com/downloads/embedded-studio/ SEGGER Embedded Studio for RISC-V] V4.12 or later
=== RAM debugging projects ===
 
The following projects are configured to demonstrate debugging of an application in the internal RAM of the SiFive FE310 MCU.
 
* [[File:SiFive_ArtyE31_Blinky_Blue_LED.zip]]
 
* [[File:SiFive_ArtyE31_Blinky_RGB_LED.zip]]
 
   
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Downloads a simple Cnt++ loop into the 64 TCM @ 0xF0000000
=== QSPI debugging projects ===
 
The following projects are configured to demonstrate debugging of an application in the external QSPI flash connected to the SiFive FE310 MCU.
 
* [[File:SiFive_ArtyE31_Blinky_Blue_LED_DebugQSPI.zip]]
 
   
== QSPI flash programming ==
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== Embedded Studio ==
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* Please make sure to install SEGGER Embedded Studio first
The J-Link software comes with a flashloader that supports programming of the external Micron 25Q128A QSPI NOR flash populated on the ARTY board. In case a different flash is used on the hardware, the flashloader needs to be modified. Please get in touch with SEGGER to obtain the source code of the flashloader to perform the necessary adaptions.
 
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* Then install the J-Link software package
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* At the end of the software package installation, you will be asked if you want to update SEGGER Embedded Studio
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* Please perform the update
   
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= Available eval boards =
== Minimum J-Link hardware requirements ==
 
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The following eval boards are available:
Please note that RISC-V is not supported by older J-Link hardware models / revisions. For an overview about which models / revisions support RISC-V: [[Software and Hardware Features Overview | List]]
 
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* [[Syntacore SCR1 SDK Arty | SCR1 SDK Arty (ARTY board)]]
   
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<references/>
== Supported FPGA images ==
 
FPGA bitstreams with debug specification v0p13 are currently supported e.g. release version v1p0.
 

Latest revision as of 13:41, 19 July 2021

The Syntacore SCR1 is a 32-bit (RV32) core, designed by Syntacore.

Requirements

  • A current J-Link model with RISC-V support
  • J-Link software V6.44d or later. Older J-Link software versions will not work.
  • The SCR1 device selection is supported since V6.44d

RTT support

As the core does not support System Bus Access (SBA), RTT is not supported for this core.

HSS access

As the core does not support System Bus Access (SBA), HSS is not supported for this core.

Limitations

  • When debugging on the Syntacore SCR1, the max. JTAG speed that can be used is 1/12 of the CPU speed, so usually fJTAG has to be <= 2 MHz. Speeds above this limit will result in unstable operation of the debug interface on the device. The device sometimes simply returns garbage status info and data on debug module accesses. This is not a limitation of J-Link but of the Syntacore SCR1

Example projects

File:Syntacore SCR1 Arty ES.zip

Requires SEGGER Embedded Studio for RISC-V V4.12 or later

Downloads a simple Cnt++ loop into the 64 TCM @ 0xF0000000

Embedded Studio

  • Please make sure to install SEGGER Embedded Studio first
  • Then install the J-Link software package
  • At the end of the software package installation, you will be asked if you want to update SEGGER Embedded Studio
  • Please perform the update

Available eval boards

The following eval boards are available: