Difference between revisions of "Syntacore SCR1"

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The Syntacore SCR1 is a 32-bit (RV32) core, designed by [https://syntacore.com/page/products/processor-ip/scr1 Syntacore].
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= Requirements =
The Syntacore SCR1 is a RISC-V based device which is supported by J-Link
 
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* A current J-Link model with RISC-V support
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* [https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack J-Link software] V6.44d or later. Older J-Link software versions will not work.
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* The SCR1 device selection is supported since V6.44d
   
= J-Link support =
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= RTT support =
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As the core does not support System Bus Access (SBA), RTT is '''not''' supported for this core.
   
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= HSS access =
== Hardware requirements ==
 
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As the core does not support System Bus Access (SBA), HSS is '''not''' supported for this core.
Please note that a current J-Link model is needed for RISC-V support: [[Software and Hardware Features Overview | Overview]]
 
 
== Software requirements ==
 
J-Link software [https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack V6.44] or later is required to support the Syntacore SCR1. Older versions will not work.
 
   
 
= Limitations =
 
= Limitations =
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* When debugging on the Syntacore SCR1, the max. JTAG speed that can be used is 1/12 of the CPU speed, so usually fJTAG has to be <= 2 MHz. Speeds above this limit will result in unstable operation of the debug interface on the device. The device sometimes simply returns garbage status info and data on debug module accesses. '''This is not a limitation of J-Link but of the Syntacore SCR1'''
== Maximum JTAG speed ==
 
When debugging on the Syntacore SCR1, the max. JTAG speed that can be used is 1/12 of the CPU speed, so usually fJTAG has to be <= 2 MHz. Speeds above this limit will result in unstable operation of the debug interface on the device. The device sometimes simply returns garbage status info and data on debug module accesses. '''This is not a limitation of J-Link but of the Syntacore SCR1'''
 
   
 
= Example projects =
 
= Example projects =
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[[File:Syntacore_SCR1_Arty_ES.zip]]
== Embedded Studio ==
 
The following example project requires [https://www.segger.com/downloads/embedded-studio/ SEGGER Embedded Studio for RISC-V]. It downloads a simple Cnt++ loop into the 64 TCM @ 0xF0000000
 
   
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Requires [https://www.segger.com/downloads/embedded-studio/ SEGGER Embedded Studio for RISC-V] V4.12 or later
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Downloads a simple Cnt++ loop into the 64 TCM @ 0xF0000000
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== Embedded Studio ==
 
* Please make sure to install SEGGER Embedded Studio first
 
* Please make sure to install SEGGER Embedded Studio first
 
* Then install the J-Link software package
 
* Then install the J-Link software package
 
* At the end of the software package installation, you will be asked if you want to update SEGGER Embedded Studio
 
* At the end of the software package installation, you will be asked if you want to update SEGGER Embedded Studio
 
* Please perform the update
 
* Please perform the update
 
* SCR1 on ARTY board: [[File:Syntacore_SCR1_Arty_ES.zip]]
 
   
 
= Available eval boards =
 
= Available eval boards =

Latest revision as of 13:41, 19 July 2021

The Syntacore SCR1 is a 32-bit (RV32) core, designed by Syntacore.

Requirements

  • A current J-Link model with RISC-V support
  • J-Link software V6.44d or later. Older J-Link software versions will not work.
  • The SCR1 device selection is supported since V6.44d

RTT support

As the core does not support System Bus Access (SBA), RTT is not supported for this core.

HSS access

As the core does not support System Bus Access (SBA), HSS is not supported for this core.

Limitations

  • When debugging on the Syntacore SCR1, the max. JTAG speed that can be used is 1/12 of the CPU speed, so usually fJTAG has to be <= 2 MHz. Speeds above this limit will result in unstable operation of the debug interface on the device. The device sometimes simply returns garbage status info and data on debug module accesses. This is not a limitation of J-Link but of the Syntacore SCR1

Example projects

File:Syntacore SCR1 Arty ES.zip

Requires SEGGER Embedded Studio for RISC-V V4.12 or later

Downloads a simple Cnt++ loop into the 64 TCM @ 0xF0000000

Embedded Studio

  • Please make sure to install SEGGER Embedded Studio first
  • Then install the J-Link software package
  • At the end of the software package installation, you will be asked if you want to update SEGGER Embedded Studio
  • Please perform the update

Available eval boards

The following eval boards are available: