Difference between revisions of "Syntacore SCR1"
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| + | The Syntacore SCR1 is a RISC-V based device which is supported by J-Link |
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| + | = J-Link support = |
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| − | '''<font color="red">TBD!!!!!!!!!!!!!!!!!</font>''' |
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| + | = Hardware requirements = |
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| − | This article describes specifics for the SiFive Arty FPGA Dev Kit. |
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| + | Please note that a current J-Link model is needed for RISC-V support: [[Software and Hardware Features Overview | Overview]] |
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| + | = Software requirements = |
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| − | == Preparing for J-Link == |
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| + | J-Link supports the Syntacore SCR1 since the following J-Link software versions: |
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| − | Syntacore provides a reference FPGA bistream for the Digilent ARTY FPGA dev kit, which allows to implement a RISC-V core. The Digilent ARTY FPGA dev kit does not come with a standard debug connector but populates the debug JTAG signals on the JD connector of the eval board. Therefore, it needs to be manually wired in case J-Link shall be connected to it. |
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| + | * Release: V6.42g or later ([https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack Download latest release]) |
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| + | * Beta: V6.43d or later ([https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPackBeta Download latest beta]) |
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| − | In the following, it is described how the pins of JD connector on the ARTY board needs to be wired to J-Link. All pins of the J-Link side refer to the standard 0.1" 20-pin connector of J-Link. |
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| + | = Example projects = |
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| − | {| class="wikitable" |
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| + | == Embedded Studio == |
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| − | |+Wiring connection |
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| + | The following example project requires SEGGER Embedded Studio for RISC-V |
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| − | ! Pin JD (ARTY) |
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| + | https://www.segger.com/downloads/embedded-studio/ |
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| − | ! Pin J-Link |
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| − | ! Description |
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| − | |- |
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| − | |7 |
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| − | |13 |
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| − | |TDO |
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| − | |- |
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| − | |3 |
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| − | |3 |
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| − | |nTRST |
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| − | |- |
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| − | |4 |
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| − | |9 |
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| − | |TCK |
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| − | |- |
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| − | |8 |
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| − | |5 |
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| − | |TDI |
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| − | |- |
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| − | |10 |
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| − | |7 |
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| − | |TMS |
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| − | |- |
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| − | |9 |
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| − | |15 |
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| − | |nRESET |
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| − | |- |
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| − | |11 |
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| − | |4 |
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| − | |GND |
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| − | |- |
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| − | |12 |
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| − | |1 |
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| − | |VTref |
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| − | |} |
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| + | '''Note''': Please make sure to install SEGGER Embedded Studio first and after that the J-Link software package. At the end of the software package installation, you will be asked if you want to update SEGGER Embedded Studio to the latest J-Link SW. Please perform the update. |
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| − | '''Note:''' The pins on the JD connector are numbered as follows: |
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| − | {| class="wikitable" |
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| − | |- |
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| − | |6 |
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| − | |5 |
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| − | |4 |
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| − | |3 |
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| − | |2 |
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| − | |1 |
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| − | |- |
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| − | |12 |
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| − | |11 |
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| − | |10 |
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| − | |9 |
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| − | |8 |
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| − | |7 |
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| − | |} |
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| − | <Photo> |
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| + | QSPI flash programming for this device is supported for the following versions: |
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| − | == Debugging in xxx == |
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| + | * V6.35g (beta) or later: [https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPackBeta Download latest beta] |
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| − | TBD |
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| − | + | * V6.36 (release) or later: [https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack Download latest release] |
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| + | '''Note:''' Currently only programming of the ISSI IS25LQ040B flash (the one mounted on the HiFive IoT board) is supported. |
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| + | = Available eval boards = |
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| − | == Minimum J-Link hardware requirements == |
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| + | The following eval boards that are based on the FE310 are available: |
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| − | Please note that RISC-V is not supported by older J-Link hardware models / revisions. For an overview about which models / revisions support RISC-V: [[Software and Hardware Features Overview | List]] |
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| + | * SiFive HiFive1 |
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| + | |||
| + | <references/> |
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Revision as of 17:22, 28 February 2019
Contents
The Syntacore SCR1 is a RISC-V based device which is supported by J-Link
J-Link support
Hardware requirements
Please note that a current J-Link model is needed for RISC-V support: Overview
Software requirements
J-Link supports the Syntacore SCR1 since the following J-Link software versions:
- Release: V6.42g or later (Download latest release)
- Beta: V6.43d or later (Download latest beta)
Example projects
Embedded Studio
The following example project requires SEGGER Embedded Studio for RISC-V https://www.segger.com/downloads/embedded-studio/
Note: Please make sure to install SEGGER Embedded Studio first and after that the J-Link software package. At the end of the software package installation, you will be asked if you want to update SEGGER Embedded Studio to the latest J-Link SW. Please perform the update.
QSPI flash programming for this device is supported for the following versions:
- V6.35g (beta) or later: Download latest beta
- V6.36 (release) or later: Download latest release
Note: Currently only programming of the ISSI IS25LQ040B flash (the one mounted on the HiFive IoT board) is supported.
Available eval boards
The following eval boards that are based on the FE310 are available:
- SiFive HiFive1
