This article describes specifics for the SiFive Arty FPGA Dev Kit.
Preparing for J-Link
Syntacore provides a reference FPGA bistream for the Digilent ARTY FPGA dev kit, which allows to implement a RISC-V core. The Digilent ARTY FPGA dev kit does not come with a standard debug connector but populates the debug JTAG signals on the JD connector of the eval board. Therefore, it needs to be manually wired in case J-Link shall be connected to it.
In the following, it is described how the pins of JD connector on the ARTY board needs to be wired to J-Link. All pins of the J-Link side refer to the standard 0.1" 20-pin connector of J-Link.
|Pin ARTY||Pin J-Link||Description|
Note: The pins on the JD connector are numbered as follows:
Debugging in FreedomStudio
Before continuing, make sure that you have J-Link software package V6.20c or later installed: Download J-Link software package
In the following, the procedure how to setup a J-Link debug session in SiFive FreedomStudio is described. This tutorial assumes that there is already a compiling project present in FreedomStudio.
If not, please find a selection of example projects here.
- Click on the arrow right next to the debug bug
- Double click on "GDB SEGGER J-Link Debugging"
- Double click the newly generated configuration
- Click on the "Debugger" tab and make sure the settings look like below (the ones with the red border are non-default ones)
- Click on the "Startup" tab and make sure the settings look like below (the ones with the red border are non-default ones)
Set program counter at
When debugging in QSPI, this option can be disabled. When debugging in RAM, it should point to the base address of region marked as executable (x) in the linker file. (Usually 0x80000000 for RAM projects)
Example projects for FreedomStudio
In the following, sample projects for the ARTY board running the SiFive FE310 MCU FPGA stream, can be downloaded.
RAM debugging projects
The following projects are configured to demonstrate debugging of an application in the internal RAM of the SiFive FE310 MCU.
QSPI debugging projects
The following projects are configured to demonstrate debugging of an application in the external QSPI flash connected to the SiFive FE310 MCU.
QSPI flash programming
The J-Link software comes with a flashloader that supports programming of the external Micron 25Q128A QSPI NOR flash populated on the ARTY board. In case a different flash is used on the hardware, the flashloader needs to be modified. Please get in touch with SEGGER to obtain the source code of the flashloader to perform the necessary adaptions.
Minimum J-Link hardware requirements
Please note that RISC-V is not supported by older J-Link hardware models / revisions. For an overview about which models / revisions support RISC-V: List
Supported FPGA images
FPGA bitstreams with debug specification v0p13 are currently supported e.g. release version v1p0.