The Syntacore SCR1 is a RISC-V based device which is supported by J-Link
Please note that a current J-Link model is needed for RISC-V support: Overview
V6.44 or later is required to support the Syntacore SCR1. Older versions will not work.
Maximum JTAG speed
When debugging on the Syntacore SCR1, the max. JTAG speed that can be used is 1/12 of the CPU speed, so usually fJTAG has to be <= 2 MHz. Speeds above this limit will result in unstable operation of the debug interface on the device. The device sometimes simply returns garbage status info and data on debug module accesses. This is not a limitation of J-Link but of the Syntacore SCR1
The following example project requires SEGGER Embedded Studio for RISC-V. It downloads a simple Cnt++ loop into the 64 TCM @ 0xF0000000
Note: Please make sure to install SEGGER Embedded Studio first and after that the J-Link software package. At the end of the software package installation, you will be asked if you want to update SEGGER Embedded Studio to the latest J-Link SW. Please perform the update.
Available eval boards
The following eval boards are available: