Difference between revisions of "Syntacore SCR3"
(Created page with "The Syntacore SCR3 is a 32-bit (RV32) core, designed by [https://syntacore.com/page/products/processor-ip/scr3 Syntacore]. __TOC__ = Requirements = * A current J-Link model...") |
|||
| Line 5: | Line 5: | ||
= Requirements = |
= Requirements = |
||
* A current J-Link model with RISC-V support |
* A current J-Link model with RISC-V support |
||
| − | * [https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack J-Link software] |
+ | * [https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack J-Link software] V7.50b or later. Older J-Link software versions will not work. |
| − | * The SCR1 device selection is supported since |
+ | * The SCR1 device selection is supported since V7.50b |
= RTT support = |
= RTT support = |
||
Revision as of 14:43, 19 July 2021
The Syntacore SCR3 is a 32-bit (RV32) core, designed by Syntacore.
Requirements
- A current J-Link model with RISC-V support
- J-Link software V7.50b or later. Older J-Link software versions will not work.
- The SCR1 device selection is supported since V7.50b
RTT support
As the core does not support System Bus Access (SBA), RTT is not supported for this core.
HSS access
As the core does not support System Bus Access (SBA), HSS is not supported for this core.
Limitations
- When debugging on the Syntacore SCR1, the max. JTAG speed that can be used is 1/12 of the CPU speed, so usually fJTAG has to be <= 2 MHz. Speeds above this limit will result in unstable operation of the debug interface on the device. The device sometimes simply returns garbage status info and data on debug module accesses. This is not a limitation of J-Link but of the Syntacore SCR1
