TI CC1354P10

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The TI CC1354 family features a powerful Cortex-M33 core with a maximum operating frequency of 48-MHz.


Internal flash

The CC1354 features up to 1024 KB internal flash. Right now, there are two different silicon revisions available for which the memory map is slightly different.

Flash layout silicon revision PG1.0:

Total flash size: 898 KB flash

Name Address Size
FLASH1 0x00000000 0x0001C000
FLASH2 0x00024000 0x00038000
FLASH3 0x00064000 0x00038000
FLASH4 0x000A4000 0x00038000
FLASH5 0x000E4000 0x0001C000

Flash layout silicon revision PG2.0:

Total flash size: 1024 KB flash

Name Address Size
FLASH 0x00000000 0x00100000

Due to the different flash layouts, the J-Link software has to support two different sector layouts for the same device / memory region. For the CC1354, this is implemented using the J-Link Multiple Flashloader feature which allows to select from a pool of different loaders for the same flash bank. By default (no loader specified), the J-Link software uses the flash layout of the PG2.0 revision. Valid loader names are:

  • CC1354P10?BankAddr=0x00000000&Loader=Silicon_Rev_PG2 --> PG2.0 flash layout
  • CC1354P10?BankAddr=0x00000000&Loader=Silicon_Rev_PG1 --> PG1.0 flash layout


The CCFG section is not part of the main flash but has it's own memory section (address 0x50000000). The CCFG section is not supported by J-Link.


A device specific reset is performed. For details, please get in contact with SEGGER.

Evaluation Boards

Example Application

  • TBD