Difference between revisions of "TMC"
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The ARM CoreSight '''T'''race '''M'''emory '''C'''ontroller (TMC) supersedes the traditional [[ETB]]. |
The ARM CoreSight '''T'''race '''M'''emory '''C'''ontroller (TMC) supersedes the traditional [[ETB]]. |
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It can be configured (at synthesization time of the device) to act as a trace capture unit that outputs trace data on dedicated trace pins (similar to traditional ETM configuration) or as a trace capture unit that stores trace data in a RAM buffer. In contrast to traditional ETB, this buffer does not have to be on-chip RAM but may also be external high-speed RAM. |
It can be configured (at synthesization time of the device) to act as a trace capture unit that outputs trace data on dedicated trace pins (similar to traditional ETM configuration) or as a trace capture unit that stores trace data in a RAM buffer. In contrast to traditional ETB, this buffer does not have to be on-chip RAM but may also be external high-speed RAM. |
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| − | There are also some other configurations possible, but not really spread in the field right now and |
+ | There are also some other configurations possible, but not really spread in the field right now and therefore not really used. |
Latest revision as of 14:56, 27 January 2021
The ARM CoreSight Trace Memory Controller (TMC) supersedes the traditional ETB. It can be configured (at synthesization time of the device) to act as a trace capture unit that outputs trace data on dedicated trace pins (similar to traditional ETM configuration) or as a trace capture unit that stores trace data in a RAM buffer. In contrast to traditional ETB, this buffer does not have to be on-chip RAM but may also be external high-speed RAM. There are also some other configurations possible, but not really spread in the field right now and therefore not really used.
