Difference between revisions of "Tracing on Silicon Labs EFR32MG12"

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(Streaming trace)
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The Silicon Labs EFR32MG12 MCU implements tracing via pins , so a J-Trace can be used for tracing.
 
The Silicon Labs EFR32MG12 MCU implements tracing via pins , so a J-Trace can be used for tracing.
   
= Minimum requirements =
+
== Minimum requirements ==
 
In order to use trace on the Silicon Labs EFR32MG12 devices, the following minimum requirements have to be met:
 
In order to use trace on the Silicon Labs EFR32MG12 devices, the following minimum requirements have to be met:
 
* J-Link software version V6.40 or later
 
* J-Link software version V6.40 or later
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* J-Trace PRO for Cortex-M HW version V1.0 or later
 
* J-Trace PRO for Cortex-M HW version V1.0 or later
   
= Sample project =
+
== Sample project ==
== Streaming trace ==
+
=== Streaming trace ===
 
The following sample project is designed to be used with J-Trace PRO and Ozone to demonstrate streaming trace. The project has been tested with the minimum requirements mentioned above and a ''WSTK Main Board BRD4001A'' evaluation board with a ''EFR32MG12'' board plugged into it. The sample project comes with a pre-configured project file for Ozone that runs out-of-the box. In order to rebuild the sample project, [https://www.segger.com/embedded-studio.html SEGGER Embedded Studio] can be used.
 
The following sample project is designed to be used with J-Trace PRO and Ozone to demonstrate streaming trace. The project has been tested with the minimum requirements mentioned above and a ''WSTK Main Board BRD4001A'' evaluation board with a ''EFR32MG12'' board plugged into it. The sample project comes with a pre-configured project file for Ozone that runs out-of-the box. In order to rebuild the sample project, [https://www.segger.com/embedded-studio.html SEGGER Embedded Studio] can be used.
   
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To create your own .JLinkScriptfile you can use the following project as reference: [https://wiki.segger.com/Tracing_on_ST_STM32F407_(SEGGER_Cortex-M_Trace_Reference_Board) Tracing on SEGGER_Cortex-M_Trace_Reference_Board]
 
To create your own .JLinkScriptfile you can use the following project as reference: [https://wiki.segger.com/Tracing_on_ST_STM32F407_(SEGGER_Cortex-M_Trace_Reference_Board) Tracing on SEGGER_Cortex-M_Trace_Reference_Board]
   
= Tested Hardware =
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== Tested Hardware ==
 
[[File:WSTK_Main_Board_BRD4001A.jpg|none|thumb|WSTK Main Board BRD4001A]]
 
[[File:WSTK_Main_Board_BRD4001A.jpg|none|thumb|WSTK Main Board BRD4001A]]
   
   
= Reference trace signal quality =
+
== Reference trace signal quality ==
 
The following pictures show oscilloscope measurements of trace signals output by the "Tested Hardware" using the example project.
 
The following pictures show oscilloscope measurements of trace signals output by the "Tested Hardware" using the example project.
 
All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes. If your trace signals look similar on your trace hardware, chances are good that tracing will work out-of-the-box using the example project.
 
All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes. If your trace signals look similar on your trace hardware, chances are good that tracing will work out-of-the-box using the example project.
 
More information about correct trace timing can be found at the following [https://www.segger.com/products/debug-probes/j-trace/technology/setting-up-trace/ website].
 
More information about correct trace timing can be found at the following [https://www.segger.com/products/debug-probes/j-trace/technology/setting-up-trace/ website].
== Rise time ==
+
=== Rise time ===
 
The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1. For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal.
 
The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1. For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal.
 
[[File:PG12_Risetime_TCLK.png|none|thumb|TCLK rise time]]
 
[[File:PG12_Risetime_TCLK.png|none|thumb|TCLK rise time]]
== Setup time ==
+
=== Setup time ===
 
The setup time shows the relative setup time between a trace data signal and trace clock. The measurement markers are set at 50% of the expected voltage level respectively. The following picture shows such a measurement for the trace data signal 0 relative to the trace clock signal.
 
The setup time shows the relative setup time between a trace data signal and trace clock. The measurement markers are set at 50% of the expected voltage level respectively. The following picture shows such a measurement for the trace data signal 0 relative to the trace clock signal.
 
[[File:PG12_Setuptime_TD0.png|none|thumb|TD0 setup time]]
 
[[File:PG12_Setuptime_TD0.png|none|thumb|TD0 setup time]]

Revision as of 17:11, 13 November 2020

This article describes how to get started with trace on the Silicon Labs EFR32MG12 MCU. This article assumes that there is already a basic knowledge about trace in general (what is trace, what different implementations of trace are there, etc.). If this is not the case, we recommend to read Trace chapter in the J-Link User Manual (UM08001). The Silicon Labs EFR32MG12 MCU implements tracing via pins , so a J-Trace can be used for tracing.

Minimum requirements

In order to use trace on the Silicon Labs EFR32MG12 devices, the following minimum requirements have to be met:

  • J-Link software version V6.40 or later
  • Ozone V2.60k or later (if streaming trace and / or the sample project from below shall be used)
  • J-Trace PRO for Cortex-M HW version V1.0 or later

Sample project

Streaming trace

The following sample project is designed to be used with J-Trace PRO and Ozone to demonstrate streaming trace. The project has been tested with the minimum requirements mentioned above and a WSTK Main Board BRD4001A evaluation board with a EFR32MG12 board plugged into it. The sample project comes with a pre-configured project file for Ozone that runs out-of-the box. In order to rebuild the sample project, SEGGER Embedded Studio can be used.

SiLabs_EFR32MG12_TraceExample.zip

Note: The example is shipped with a compiled .JLinkScriptfile, should you need the original source, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/.

To create your own .JLinkScriptfile you can use the following project as reference: Tracing on SEGGER_Cortex-M_Trace_Reference_Board

Tested Hardware

WSTK Main Board BRD4001A


Reference trace signal quality

The following pictures show oscilloscope measurements of trace signals output by the "Tested Hardware" using the example project. All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes. If your trace signals look similar on your trace hardware, chances are good that tracing will work out-of-the-box using the example project. More information about correct trace timing can be found at the following website.

Rise time

The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1. For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal.

TCLK rise time

Setup time

The setup time shows the relative setup time between a trace data signal and trace clock. The measurement markers are set at 50% of the expected voltage level respectively. The following picture shows such a measurement for the trace data signal 0 relative to the trace clock signal.

TD0 setup time