Using RTT on RZ A1H

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This page explains how to use SEGGER Real-Time-Terminal (RTT) on the Renesas RZ/A1H family devices. As the setup on the target project side is slightly different from IDE to IDE, in the following some sample setups for different IDEs are explained.

SEGGER Embedded Studio

There is a sample project for Embedded Studio available that demonstrates how to configure the project + target application for using RTT with Renesas RZ/A1H. The sample project can be downloaded here: xxxxxxxxxxxxxxxxxxxxxxx

Required components

The following are the minimum requirements to use RTT on the Renesas RZ:

  1. Embedded Studio


The Renesas RZ/G1 is a dual core device. There are two variants of the RZ/G1:

  • RZ/G1E dual core Cortex-A7
  • RZ/G1M dual core Cortex-A15

By default, only one core (main core) is running which needs to release the second core from reset from within the application running on the main core.

Due to design limitations of the device, the second core cannot be easily enabled independently from the main core, via J-Link.

Dual core debugging on the RZ/G1

In order to debug both cores on the RZ/G1, the following needs to be done:

  1. Start a debug session for the main core, which uses the appropriate ConnectCore0 script
  2. Once the debug session has been started, it will have the second core enabled for debugging
  3. Start a debug session for the second core, which uses the appropriate ConnectCore1 script
  4. From now on, both cores can be debugged in parallel in both debugger instances

Script Files and sample projects

Below some sample script files for the dual core debugging as well as some sample projects for emIDE (V2.20 or later) and IAR EWARM (V7.40 or later) are available for download