Difference between revisions of "emCrypt"

From SEGGER Wiki
Jump to: navigation, search
m
m
Line 20: Line 20:
 
! scope="col" class="unsortable" | Link
  
! scope="col" class="unsortable" | Link
 
|-
  
|-
−
| ECDSA sign and verify || STM32F072 || CM0 || 48 MHz || No || All NIST and Brainpool prime curves || [[ECDSA_Sign_Verify_STM32F072|Results]]
 +
| ECDSA sign and verify || STM32F072 || CM0 || 48 MHz || No || Run from flash, data in internal RAM || [[ECDSA_Sign_Verify_STM32F072|Results]]
 
|-
  
|-
−
| ECDSA sign and verify || R7FS124 || CM0 || 24 MHz || No || All NIST and Brainpool prime curves || [[ECDSA_Sign_Verify_R7FS124|Results]]
 +
| ECDSA sign and verify || R7FS124 || CM0 || 24 MHz || No || Run from flash, data in internal RAM || [[ECDSA_Sign_Verify_R7FS124|Results]]
 
|-
  
|-
−
| ECDSA sign and verify || MK66FN2M0 || CM4 || 168 MHz || No || All NIST and Brainpool prime curves|| [[ECDSA_Sign_Verify_MK66FN2M0|Results]]
 +
| ECDSA sign and verify || MK66FN2M0 || CM4 || 168 MHz || No || Run from flash, data in internal RAM || [[ECDSA_Sign_Verify_MK66FN2M0|Results]]
 
|-
  
|-
−
| ECDSA sign and verify || STM32F746 || CM7 || 200 MHz || No || All NIST and Brainpool prime curves|| [[ECDSA_Sign_Verify_STM32F746|Results]]
 +
| ECDSA sign and verify || STM32F746 || CM7 || 200 MHz || No || Run from flash, data in internal RAM || [[ECDSA_Sign_Verify_STM32F746|Results]]
 
|-
  
|-
 
| ECDSA sign and verify || AT91SAM9263 || ARM926 || 200 MHz || No || Run from SDRAM with cache enabled || [[ECDSA_Sign_Verify_AT91SAM9263|Results]]
  
| ECDSA sign and verify || AT91SAM9263 || ARM926 || 200 MHz || No || Run from SDRAM with cache enabled || [[ECDSA_Sign_Verify_AT91SAM9263|Results]]
 
|-
  
|-
−
| EdDSA sign and verify || MK66FN2M0 || CM4 || 168 MHz || No || Ed25519 and Ed448 || [[EdDSA_Sign_Verify_MK66FN2M0|Results]]
 +
| EdDSA sign and verify || MK66FN2M0 || CM4 || 168 MHz || No || Run from flash, data in internal RAM || [[EdDSA_Sign_Verify_MK66FN2M0|Results]]
 
|-
  
|-
−
| EdDSA sign and verify || STM32F746 || CM7 || 200 MHz || No || Ed25519 and Ed448 || [[EdDSA_Sign_Verify_STM32F746|Results]]
 +
| EdDSA sign and verify || STM32F746 || CM7 || 200 MHz || No || Run from flash, data in internal RAM || [[EdDSA_Sign_Verify_STM32F746|Results]]
 
|-
  
|-
 
| EdDSA sign and verify || AT91SAM9263 || ARM926 || 200 MHz || No || Run from SDRAM with cache enabled || [[EdDSA_Sign_Verify_AT91SAM9263|Results]]
  
| EdDSA sign and verify || AT91SAM9263 || ARM926 || 200 MHz || No || Run from SDRAM with cache enabled || [[EdDSA_Sign_Verify_AT91SAM9263|Results]]
 
|-
  
|-
−
| Hash algorithms || MK66FN2M0 || CM4 || 168 MHz || Yes || MD5, RIPEMD160, SHA-1, SHA-256, SHA-512, SM3 || [[Hash_MK66FN2M0|Results]]
 +
| Hash algorithms || MK66FN2M0 || CM4 || 168 MHz || Yes || Run from flash, data in internal RAM || [[Hash_MK66FN2M0|Results]]
 
|-
  
|-
−
| Hash algorithms || STM32F746 || CM7 || 200 MHz || No || MD5, RIPEMD160, SHA-1, SHA-256, SHA-512, SM3 || [[Hash_STM32F746|Results]]
 +
| Hash algorithms || STM32F746 || CM7 || 200 MHz || No || Run from flash, data in internal RAM || [[Hash_STM32F746|Results]]
  +
|-
  +
| Hash algorithms || STM32F756 || CM7 || 200 MHz || Yes || Run from flash, data in internal RAM || [[Hash_STM32F746|Results]]
 
|-
  
|-
 
| Hash algorithms || AT91SAM9263 || ARM926 || 200 MHz || No || Run from SDRAM with cache enabled || [[Hash_AT91SAM9263|Results]]
  
| Hash algorithms || AT91SAM9263 || ARM926 || 200 MHz || No || Run from SDRAM with cache enabled || [[Hash_AT91SAM9263|Results]]
 
|-
  
|-
−
| MAC algorithms || STM32F746 || CM7 || 200 MHz || No || CMAC, GMAC, HMAC, Poly1305 || [[MAC_STM32F746|Results]]
 +
| MAC algorithms || STM32F746 || CM7 || 200 MHz || No || Run from flash, data in internal RAM || [[MAC_STM32F746|Results]]
 
|-
  
|-
 
| MAC algorithms || AT91SAM9263 || ARM926 || 200 MHz || No || Run from SDRAM with cache enabled || [[MAC_ATSAM9263|Results]]
  
| MAC algorithms || AT91SAM9263 || ARM926 || 200 MHz || No || Run from SDRAM with cache enabled || [[MAC_ATSAM9263|Results]]
Line 50: Line 52:
 
| Cipher (AES) || AT91SAM9263 || ARM926 || 200 MHz || No || Run from SDRAM with cache enabled || [[AES_ATSAM9263|Results]]
  
| Cipher (AES) || AT91SAM9263 || ARM926 || 200 MHz || No || Run from SDRAM with cache enabled || [[AES_ATSAM9263|Results]]
 
|-
  
|-
−
| Cipher (AES) || STM32F756 || CM7 || 200 MHz || Yes || Run from flash, use internal RAM || [[AES_STM32F756|Results]]
 +
| Cipher (AES) || STM32F756 || CM7 || 200 MHz || Yes || Run from flash, data in internal RAM || [[AES_STM32F756|Results]]
 
|-
  
|-
 
|}
  
|}

Revision as of 16:56, 8 July 2019

emCrypt is a secure and efficient implementation of essential cryptographic algorithms specifically designed for embedded systems.

This wiki page explains and links to other articles providing information too specific for the user manual or product pages on www.segger.com

Contents

Performance

Cryptography benchmarks on real hardware
Benchmark Device Core Speed HW Accel Notes Link
ECDSA sign and verify STM32F072 CM0 48 MHz No Run from flash, data in internal RAM Results
ECDSA sign and verify R7FS124 CM0 24 MHz No Run from flash, data in internal RAM Results
ECDSA sign and verify MK66FN2M0 CM4 168 MHz No Run from flash, data in internal RAM Results
ECDSA sign and verify STM32F746 CM7 200 MHz No Run from flash, data in internal RAM Results
ECDSA sign and verify AT91SAM9263 ARM926 200 MHz No Run from SDRAM with cache enabled Results
EdDSA sign and verify MK66FN2M0 CM4 168 MHz No Run from flash, data in internal RAM Results
EdDSA sign and verify STM32F746 CM7 200 MHz No Run from flash, data in internal RAM Results
EdDSA sign and verify AT91SAM9263 ARM926 200 MHz No Run from SDRAM with cache enabled Results
Hash algorithms MK66FN2M0 CM4 168 MHz Yes Run from flash, data in internal RAM Results
Hash algorithms STM32F746 CM7 200 MHz No Run from flash, data in internal RAM Results
Hash algorithms STM32F756 CM7 200 MHz Yes Run from flash, data in internal RAM Results
Hash algorithms AT91SAM9263 ARM926 200 MHz No Run from SDRAM with cache enabled Results
MAC algorithms STM32F746 CM7 200 MHz No Run from flash, data in internal RAM Results
MAC algorithms AT91SAM9263 ARM926 200 MHz No Run from SDRAM with cache enabled Results
RSA (ModExp) AT91SAM9263 ARM926 200 MHz No Run from SDRAM with cache enabled Results
Cipher (AES) AT91SAM9263 ARM926 200 MHz No Run from SDRAM with cache enabled Results
Cipher (AES) STM32F756 CM7 200 MHz Yes Run from flash, data in internal RAM Results
Retrieved from "https://wiki.segger.com/index.php?title=emCrypt&oldid=5711"