embOS:MPU on CortexM
With embOS-MPU different memory regions with separate access rights and memory attributes can be defined. A memory region can be added with OS_MPU_AddRegion().
void OS_MPU_AddRegion(OS_TASK* pTask, OS_U32 BaseAddr, OS_U32 Size, OS_U32 Permissions, OS_U32 Attributes);
embOS-MPU includes defines for the permissions like OS_MPU_READONLY but not for the attributes since they are core specific.
ARMv7-M Memory Attributes
The Cortex-M memory attributes include the following bits:
Bufferable: Write to memory can be carried out by a write buffer while the processor continues on next instruction execution.
Cacheable: Data obtained from memory read can be copied to a memory cache so that next time it is accessed the value can be obtained from the cache to speed up the program execution.
Sharable: Data in this memory region could be shared by multiple bus masters. Memory system needs to ensure coherency of data between different bus masters in shareable memory region.
TEX: Type Extension field
These bits are implemented in the Cortex-M MPU Region Base Attribute and Size Register (0xE000EDA0):
31:29 Reserved 28 XN R/W — Instruction Access Disable (1 = disable instruction fetch from this region; an attempt to do so will result in a memory management fault) 27 Reserved 26:24 AP R/W — Data Access Permission field 23:22 Reserved 21:19 TEX R/W — Type Extension field 18 S R/W — Shareable 17 C R/W — Cacheable 16 B R/W — Bufferable 15:8 SRD R/W — Subregion disable 7:6 Reserved 5:1 REGION SIZE R/W — MPU Protection Region size 0 ENABLE R/W — Region enable
TEX C B Description Region Shareability b000 0 0 Strongly ordered (transfers carry out and complete in programmed order) Shareable b000 0 1 Shared device (write can be buffered) Shareable b000 1 0 Outer and inner write-through; no write allocate [S] b000 1 1 Outer and inner write-back; no write allocate [S] b001 0 0 Outer and inner non cacheable [S] b001 0 1 Reserved Reserved b001 1 0 Implementation defined – b001 1 1 Outer and inner write-back; write and read allocate [S] b010 0 0 Nonshared device Not shared b010 0 1 Reserved Reserved b010 1 X Reserved Reserved b1BB A A Cached memory; BB = outer policy, AA = inner policy [S]
Encoding of Inner and Outer Cache Policy when Most Significant Bit of TEX Is Set to 1:
Memory Attribute Encoding (AA and BB) Cache Policy 00 Noncacheable 01 Write back, write, and read allocate 10 Write through, no write allocate 11 Write back, no write allocate
With embOS-MPU Cortex-M the Attributes parameter is shifted by 16 bits and set in the Cortex-M Region Base Attribute and Size Register.
Setting the memory attribute of a region to Write back, no write allocate: #define TEX_100 (4u << 3) #define CACHEABLE (1u << 1) #define BUFFERABLE (1u << 0) OS_MPU_AddRegion(&HPTask, 0x00, 0x2000, OS_MPU_READONLY, TEX_100 | BUFFERABLE | CACHEABLE);