Difference between revisions of "embOS MPU on CortexM"

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With embOS-MPU different memory regions with separate access rights and memory attributes can be defined.
embOS is a priority-controlled real-time operating system, designed to be used as foundation for the development of embedded applications.
 
  +
A memory region can be added with ''OS_MPU_AddRegion()''.
   
  +
__TOC__
== FAQ ==
 
'''I want use the Cortex-M memory attributes with embOS-MPU Cortex-M'''
 
   
  +
=== OS_MPU_AddRegion() ===
The Cortex-M memory attributes include the following bits:
 
  +
''OS_MPU_AddRegion()'' has the following prototype:
   
  +
<source lang="C">
''Bufferable:''
 
  +
void OS_MPU_AddRegion(OS_TASK* pTask,
Write to memory can be carried out by a write buffer while the processor continues on next instruction execution.
 
  +
OS_U32 BaseAddr,
  +
OS_U32 Size,
  +
OS_U32 Permissions,
  +
OS_U32 Attributes);
  +
</source>
   
  +
=== ARMv7-M Memory Attributes ===
''Cacheable:''
 
  +
embOS-MPU includes defines for the permissions (e.g. ''OS_MPU_READONLY''), but not for the attributes since they are core specific.
Data obtained from memory read can be copied to a memory cache so that next time it is accessed the value can be obtained from the cache to speed up the program execution.
 
   
  +
The Cortex-M memory attributes include the following bits:
''Sharable:''
 
  +
{| class="wikitable"
Data in this memory region could be shared by multiple bus masters. Memory system needs to ensure coherency of data between different bus masters in shareable memory region.
 
  +
|-
 
  +
| Bufferable || Write to memory can be carried out by a write buffer while the processor continues on next instruction execution.
''TEX:''
 
  +
|-
Type Extension field
 
  +
| Cacheable || Data obtained from memory read can be copied to a memory cache so that next time it is accessed the value can be obtained from the cache to speed up the program execution.
  +
|-
  +
| Sharable || Data in this memory region could be shared by multiple bus masters. Memory system needs to ensure coherency of data between different bus masters in shareable memory region.
  +
|-
  +
| TEX || Type Extension field
  +
|}
   
 
These bits are implemented in the Cortex-M MPU Region Base Attribute and Size Register (0xE000EDA0):
 
These bits are implemented in the Cortex-M MPU Region Base Attribute and Size Register (0xE000EDA0):
  +
31:29 Reserved
<nowiki>
 
  +
28 XN R/W — Instruction Access Disable (1 = disable instruction fetch from this region; an attempt to do so will result in a memory management fault)
31:29 Reserved
 
  +
27 Reserved
28 XN R/W — Instruction Access Disable (1 = disable instruction fetch from this region; an attempt to do so will result in a memory management fault)
 
  +
26:24 AP R/W — Data Access Permission field
27 Reserved
 
  +
23:22 Reserved
26:24 AP R/W — Data Access Permission field
 
  +
21:19 TEX R/W — Type Extension field
23:22 Reserved
 
21:19 TEX R/W — Type Extension field
+
18 S R/W — Shareable
18 S R/W — Shareable
+
17 C R/W — Cacheable
17 C R/W — Cacheable
+
16 B R/W — Bufferable
16 B R/W — Bufferable
+
15:8 SRD R/W — Subregion disable
  +
7:6 Reserved
15:8 SRD R/W — Subregion disable
 
  +
5:1 REGION SIZE R/W — MPU Protection Region size
7:6 Reserved
 
5:1 REGION SIZE R/W — MPU Protection Region size
+
0 ENABLE R/W — Region enable
0 ENABLE R/W — Region enable
 
</nowiki>
 
   
  +
Possible values are:
   
  +
{| class="wikitable"
Encoding of Inner and Outer Cache Policy When Most Significant Bit of TEX Is Set to 1
 
  +
|-
<nowiki>
 
  +
! colspan="4" | Settings || rowspan="66" | || colspan="3" | Resulting attributes
Memory Attribute Encoding (AA and BB) Cache Policy
 
  +
|-
00 Noncacheable
 
  +
! TEX || C || B || S || Memory Type || Shareability || Other attributes
01 Write back, write, and read allocate
 
  +
|- style="vertical-align:middle;"
10 Write through, no write allocate
 
  +
| rowspan="8" | 000
11 Write back, no write allocate
 
  +
| rowspan="4" | 0
</nowiki>
 
  +
| rowspan="2" | 0
  +
| 0
  +
| rowspan="2" | Strongly ordered
  +
| rowspan="4" | Shareable<ref name="SBit">The value of the S-bit is ignored in this encoding.</ref>
  +
| rowspan="4" | -
  +
|- style="vertical-align:middle;"
  +
| 1
  +
|- style="vertical-align:middle;"
  +
| rowspan="2" | 1
  +
| 0
  +
| rowspan="2" | Device
  +
|- style="vertical-align:middle;"
  +
| 1
  +
|- style="vertical-align:middle;"
  +
| rowspan="4" | 1
  +
| rowspan="2" | 0
  +
| 0
  +
| rowspan="6" | Normal
  +
| Not shareable
  +
| rowspan="2" | Outer write through, no write allocate<br />Inner write through, no write allocate
  +
|- style="vertical-align:middle;"
  +
| 1
  +
| Shareable
  +
|- style="vertical-align:middle;"
  +
| rowspan="2" | 1
  +
| 0
  +
| Not shareable
  +
| rowspan="2" | Outer write back, no write allocate<br />Inner write back, no write allocate
  +
|- style="vertical-align:middle;"
  +
| 1
  +
| Shareable
  +
|- style="vertical-align:middle;"
  +
| rowspan="8" | 001
  +
| rowspan="4" | 0
  +
| rowspan="2" | 0
  +
| 0
  +
| Not shareable
  +
| rowspan="2" | Outer noncacheable<br />Inner noncacheable
  +
|- style="vertical-align:middle;"
  +
| 1
  +
| Shareable
  +
|- style="vertical-align:middle;"
  +
| rowspan="2" | 1
  +
| 0
  +
| rowspan="2" colspan="3" style="text-align:center;" | Reserved encoding
  +
|- style="vertical-align:middle;"
  +
| 1
  +
|- style="vertical-align:middle;"
  +
| rowspan="4" | 1
  +
| rowspan="2" | 0
  +
| 0
  +
| rowspan="2" colspan="3" style="text-align:center;" | Implementation defined encoding
  +
|- style="vertical-align:middle;"
  +
| 1
  +
|- style="vertical-align:middle;"
  +
| rowspan="2" | 1
  +
| 0
  +
| rowspan="2" | Normal
  +
| Not shareable
  +
| rowspan="2" | Outer write back, write and read allocate<br />Inner write back, write and read allocate
  +
|- style="vertical-align:middle;"
  +
| 1
  +
| Shareable
  +
|- style="vertical-align:middle;"
  +
| rowspan="8" | 010
  +
| rowspan="4" | 0
  +
| rowspan="2" | 0
  +
| 0
  +
| rowspan="2" | Device
  +
| rowspan="2" | Not shareable<ref name="SBit" />
  +
| rowspan="2" | -
  +
|- style="vertical-align:middle;"
  +
| 1
  +
|- style="vertical-align:middle;"
  +
| rowspan="2" | 1
  +
| 0
  +
| rowspan="14" colspan="3" style="text-align:center;" | Reserved encoding
  +
|- style="vertical-align:middle;"
  +
| 1
  +
|- style="vertical-align:middle;"
  +
| rowspan="4" | 1
  +
| rowspan="2" | 0
  +
| 0
  +
|- style="vertical-align:middle;"
  +
| 1
  +
|- style="vertical-align:middle;"
  +
| rowspan="2" | 1
  +
| 0
  +
|- style="vertical-align:middle;"
  +
| 1
  +
|-
  +
|- style="vertical-align:middle;"
  +
| rowspan="8" | 011
  +
| rowspan="4" | 0
  +
| rowspan="2" | 0
  +
| 0
  +
|- style="vertical-align:middle;"
  +
| 1
  +
|- style="vertical-align:middle;"
  +
| rowspan="2" | 1
  +
| 0
  +
|- style="vertical-align:middle;"
  +
| 1
  +
|- style="vertical-align:middle;"
  +
| rowspan="4" | 1
  +
| rowspan="2" | 0
  +
| 0
  +
|- style="vertical-align:middle;"
  +
| 1
  +
|- style="vertical-align:middle;"
  +
| rowspan="2" | 1
  +
| 0
  +
|- style="vertical-align:middle;"
  +
| 1
  +
|-
  +
| rowspan="8" | 100
  +
| rowspan="4" | 0
  +
| rowspan="2" | 0
  +
| 0
  +
| rowspan="32" | Normal
  +
| Not shareable
  +
| rowspan="2" | Outer noncacheable<br />Inner noncacheable
  +
|-
  +
| 1
  +
| Shareable
  +
|-
  +
| rowspan="2" | 1
  +
| 0
  +
| Not shareable
  +
| rowspan="2" | Outer noncacheable<br />Inner write back, write and read allocate
  +
|-
  +
| 1
  +
| Shareable
  +
|-
  +
| rowspan="4" | 1
  +
| rowspan="2" | 0
  +
| 0
  +
| Not shareable
  +
| rowspan="2" | Outer noncacheable<br />Inner write through, no write allocate
  +
|-
  +
| 1
  +
| Shareable
  +
|-
  +
| rowspan="2" | 1
  +
| 0
  +
| Not shareable
  +
| rowspan="2" | Outer noncacheable<br />Inner write back, no write allocate
  +
|-
  +
| 1
  +
| Shareable
  +
|-
  +
| rowspan="8" | 101
  +
| rowspan="4" | 0
  +
| rowspan="2" | 0
  +
| 0
  +
| Not shareable
  +
| rowspan="2" | Outer write back, write and read allocate<br />Inner noncacheable
  +
|-
  +
| 1
  +
| Shareable
  +
|-
  +
| rowspan="2" | 1
  +
| 0
  +
| Not shareable
  +
| rowspan="2" | Outer write back, write and read allocate<br />Inner write back, write and read allocate
  +
|-
  +
| 1
  +
| Shareable
  +
|-
  +
| rowspan="4" | 1
  +
| rowspan="2" | 0
  +
| 0
  +
| Not shareable
  +
| rowspan="2" | Outer write back, write and read allocate<br />Inner write through, no write allocate
  +
|-
  +
| 1
  +
| Shareable
  +
|-
  +
| rowspan="2" | 1
  +
| 0
  +
| Not shareable
  +
| rowspan="2" | Outer write back, write and read allocate<br />Inner write back, no write allocate
  +
|-
  +
| 1
  +
| Shareable
  +
|-
  +
| rowspan="8" | 110
  +
| rowspan="4" | 0
  +
| rowspan="2" | 0
  +
| 0
  +
| Not shareable
  +
| rowspan="2" | Outer write through, no write allocate<br />Inner noncacheable
  +
|-
  +
| 1
  +
| Shareable
  +
|-
  +
| rowspan="2" | 1
  +
| 0
  +
| Not shareable
  +
| rowspan="2" | Outer write through, no write allocate<br />Inner write back, write and read allocate
  +
|-
  +
| 1
  +
| Shareable
  +
|-
  +
| rowspan="4" | 1
  +
| rowspan="2" | 0
  +
| 0
  +
| Not shareable
  +
| rowspan="2" | Outer write through, no write allocate<br />Inner write through, no write allocate
  +
|-
  +
| 1
  +
| Shareable
  +
|-
  +
| rowspan="2" | 1
  +
| 0
  +
| Not shareable
  +
| rowspan="2" | Outer write through, no write allocate<br />Inner write back, no write allocate
  +
|-
  +
| 1
  +
| Shareable
  +
|-
  +
| rowspan="8" | 111
  +
| rowspan="4" | 0
  +
| rowspan="2" | 0
  +
| 0
  +
| Not shareable
  +
| rowspan="2" | Outer write back, no write allocate<br />Inner noncacheable
  +
|-
  +
| 1
  +
| Shareable
  +
|-
  +
| rowspan="2" | 1
  +
| 0
  +
| Not shareable
  +
| rowspan="2" | Outer write back, no write allocate<br />Inner write back, write and read allocate
  +
|-
  +
| 1
  +
| Shareable
  +
|-
  +
| rowspan="4" | 1
  +
| rowspan="2" | 0
  +
| 0
  +
| Not shareable
  +
| rowspan="2" | Outer write back, no write allocate<br />Inner write through, no write allocate
  +
|-
  +
| 1
  +
| Shareable
  +
|-
  +
| rowspan="2" | 1
  +
| 0
  +
| Not shareable
  +
| rowspan="2" | Outer write back, no write allocate<br />Inner write back, no write allocate
  +
|-
  +
| 1
  +
| Shareable
  +
|}
  +
<references/>
   
  +
With embOS-MPU Cortex-M the ''Attributes'' parameter is shifted by 16 bits and set in the Cortex-M Region Base Attribute and Size Register.
These bits can be set for every MPU region with OS_MPU_AddRegion().
 
   
  +
=== Example ===
OS_MPU_AddRegion() prototype:
 
<nowiki>
 
void OS_MPU_AddRegion(OS_TASK* pTask,
 
OS_U32 BaseAddr,
 
OS_U32 Size,
 
OS_U32 Permissions,
 
OS_U32 Attributes);
 
</nowiki>
 
 
With embOS-MPU Cortex-M the ''Attribute'' parameter is shifted by 16 bits and set in the Coretx-M Region Base Attribute and Size Register.
 
 
Example:
 
<nowiki>
 
 
Setting the memory attribute of a region to Write back, no write allocate:
 
Setting the memory attribute of a region to Write back, no write allocate:
   
  +
<source lang="C">
#define TEX_100 (4u << 19)
 
  +
#define TEX_100 (4u << 3)
 
#define CACHEABLE (1u << 1)
 
#define CACHEABLE (1u << 1)
 
#define BUFFERABLE (1u << 0)
 
#define BUFFERABLE (1u << 0)
   
 
OS_MPU_AddRegion(&HPTask, 0x00, 0x2000, OS_MPU_READONLY, TEX_100 | BUFFERABLE | CACHEABLE);
 
OS_MPU_AddRegion(&HPTask, 0x00, 0x2000, OS_MPU_READONLY, TEX_100 | BUFFERABLE | CACHEABLE);
  +
</source>
 
</nowiki>
 

Latest revision as of 09:27, 29 June 2021

With embOS-MPU different memory regions with separate access rights and memory attributes can be defined. A memory region can be added with OS_MPU_AddRegion().

OS_MPU_AddRegion()

OS_MPU_AddRegion() has the following prototype:

void OS_MPU_AddRegion(OS_TASK* pTask,
                      OS_U32   BaseAddr,
                      OS_U32   Size,
                      OS_U32   Permissions,
                      OS_U32   Attributes);

ARMv7-M Memory Attributes

embOS-MPU includes defines for the permissions (e.g. OS_MPU_READONLY), but not for the attributes since they are core specific.

The Cortex-M memory attributes include the following bits:

Bufferable Write to memory can be carried out by a write buffer while the processor continues on next instruction execution.
Cacheable Data obtained from memory read can be copied to a memory cache so that next time it is accessed the value can be obtained from the cache to speed up the program execution.
Sharable Data in this memory region could be shared by multiple bus masters. Memory system needs to ensure coherency of data between different bus masters in shareable memory region.
TEX Type Extension field

These bits are implemented in the Cortex-M MPU Region Base Attribute and Size Register (0xE000EDA0):

31:29       Reserved
28          XN            R/W         — Instruction Access Disable (1 = disable instruction fetch from this region; an attempt to do so will result in a memory management fault)
27          Reserved
26:24       AP            R/W         — Data Access Permission field
23:22       Reserved
21:19       TEX           R/W         — Type Extension field
18          S             R/W         — Shareable
17          C             R/W         — Cacheable
16          B             R/W         — Bufferable
15:8        SRD           R/W         — Subregion disable
7:6         Reserved
5:1         REGION SIZE   R/W         — MPU Protection Region size
0           ENABLE        R/W         — Region enable

Possible values are:

Settings Resulting attributes
TEX C B S Memory Type Shareability Other attributes
000 0 0 0 Strongly ordered Shareable[1] -
1
1 0 Device
1
1 0 0 Normal Not shareable Outer write through, no write allocate
Inner write through, no write allocate
1 Shareable
1 0 Not shareable Outer write back, no write allocate
Inner write back, no write allocate
1 Shareable
001 0 0 0 Not shareable Outer noncacheable
Inner noncacheable
1 Shareable
1 0 Reserved encoding
1
1 0 0 Implementation defined encoding
1
1 0 Normal Not shareable Outer write back, write and read allocate
Inner write back, write and read allocate
1 Shareable
010 0 0 0 Device Not shareable[1] -
1
1 0 Reserved encoding
1
1 0 0
1
1 0
1
011 0 0 0
1
1 0
1
1 0 0
1
1 0
1
100 0 0 0 Normal Not shareable Outer noncacheable
Inner noncacheable
1 Shareable
1 0 Not shareable Outer noncacheable
Inner write back, write and read allocate
1 Shareable
1 0 0 Not shareable Outer noncacheable
Inner write through, no write allocate
1 Shareable
1 0 Not shareable Outer noncacheable
Inner write back, no write allocate
1 Shareable
101 0 0 0 Not shareable Outer write back, write and read allocate
Inner noncacheable
1 Shareable
1 0 Not shareable Outer write back, write and read allocate
Inner write back, write and read allocate
1 Shareable
1 0 0 Not shareable Outer write back, write and read allocate
Inner write through, no write allocate
1 Shareable
1 0 Not shareable Outer write back, write and read allocate
Inner write back, no write allocate
1 Shareable
110 0 0 0 Not shareable Outer write through, no write allocate
Inner noncacheable
1 Shareable
1 0 Not shareable Outer write through, no write allocate
Inner write back, write and read allocate
1 Shareable
1 0 0 Not shareable Outer write through, no write allocate
Inner write through, no write allocate
1 Shareable
1 0 Not shareable Outer write through, no write allocate
Inner write back, no write allocate
1 Shareable
111 0 0 0 Not shareable Outer write back, no write allocate
Inner noncacheable
1 Shareable
1 0 Not shareable Outer write back, no write allocate
Inner write back, write and read allocate
1 Shareable
1 0 0 Not shareable Outer write back, no write allocate
Inner write through, no write allocate
1 Shareable
1 0 Not shareable Outer write back, no write allocate
Inner write back, no write allocate
1 Shareable
  1. 1.0 1.1 The value of the S-bit is ignored in this encoding.

With embOS-MPU Cortex-M the Attributes parameter is shifted by 16 bits and set in the Cortex-M Region Base Attribute and Size Register.

Example

Setting the memory attribute of a region to Write back, no write allocate:

#define TEX_100    (4u << 3)
#define CACHEABLE  (1u << 1)
#define BUFFERABLE (1u << 0)

OS_MPU_AddRegion(&HPTask, 0x00, 0x2000, OS_MPU_READONLY, TEX_100 | BUFFERABLE | CACHEABLE);