Difference between revisions of "embOS MPU on CortexM"

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With embOS-MPU different memory regions with separate access rights and memory attributes can be defined.
 
With embOS-MPU different memory regions with separate access rights and memory attributes can be defined.
A memory region can be added with OS_MPU_AddRegion().
+
A memory region can be added with ''OS_MPU_AddRegion()''.
   
  +
__TOC__
'''OS_MPU_AddRegion() prototype:'''
 
   
  +
=== OS_MPU_AddRegion() ===
<nowiki>
 
  +
''OS_MPU_AddRegion()'' has the following prototype:
  +
  +
<source lang="C">
 
void OS_MPU_AddRegion(OS_TASK* pTask,
 
void OS_MPU_AddRegion(OS_TASK* pTask,
 
OS_U32 BaseAddr,
 
OS_U32 BaseAddr,
Line 10: Line 13:
 
OS_U32 Permissions,
 
OS_U32 Permissions,
 
OS_U32 Attributes);
 
OS_U32 Attributes);
</nowiki>
+
</source>
   
  +
=== ARMv7-M Memory Attributes ===
embOS-MPU includes defines for the permissions like ''OS_MPU_READONLY'' but not for the attributes since they are core specific.
 
  +
embOS-MPU includes defines for the permissions (e.g. ''OS_MPU_READONLY''), but not for the attributes since they are core specific.
 
'''ARMv7-M Memory Attributes'''
 
   
 
The Cortex-M memory attributes include the following bits:
 
The Cortex-M memory attributes include the following bits:
  +
{| class="wikitable"
  +
|-
  +
| Bufferable || Write to memory can be carried out by a write buffer while the processor continues on next instruction execution.
  +
|-
  +
| Cacheable || Data obtained from memory read can be copied to a memory cache so that next time it is accessed the value can be obtained from the cache to speed up the program execution.
  +
|-
  +
| Sharable || Data in this memory region could be shared by multiple bus masters. Memory system needs to ensure coherency of data between different bus masters in shareable memory region.
  +
|-
  +
| TEX || Type Extension field
  +
|}
   
  +
These bits are implemented in the Cortex-M MPU Region Base Attribute and Size Register (0xE000EDA0):
''Bufferable:''
 
  +
31:29 Reserved
Write to memory can be carried out by a write buffer while the processor continues on next instruction execution.
 
  +
28 XN R/W — Instruction Access Disable (1 = disable instruction fetch from this region; an attempt to do so will result in a memory management fault)
  +
27 Reserved
  +
26:24 AP R/W — Data Access Permission field
  +
23:22 Reserved
  +
21:19 TEX R/W — Type Extension field
  +
18 S R/W — Shareable
  +
17 C R/W — Cacheable
  +
16 B R/W — Bufferable
  +
15:8 SRD R/W — Subregion disable
  +
7:6 Reserved
  +
5:1 REGION SIZE R/W — MPU Protection Region size
  +
0 ENABLE R/W — Region enable
   
  +
Permissible values are:
''Cacheable:''
 
Data obtained from memory read can be copied to a memory cache so that next time it is accessed the value can be obtained from the cache to speed up the program execution.
 
   
  +
TEX C B Description Region Shareability
''Sharable:''
 
  +
b000 0 0 Strongly ordered (transfers carry out and complete in programmed order) Shareable
Data in this memory region could be shared by multiple bus masters. Memory system needs to ensure coherency of data between different bus masters in shareable memory region.
 
  +
b000 0 1 Shared device (write can be buffered) Shareable
  +
b000 1 0 Outer and inner write-through; no write allocate [S]
  +
b000 1 1 Outer and inner write-back; no write allocate [S]
  +
b001 0 0 Outer and inner non cacheable [S]
  +
b001 0 1 Reserved Reserved
  +
b001 1 0 Implementation defined –
  +
b001 1 1 Outer and inner write-back; write and read allocate [S]
  +
b010 0 0 Nonshared device Not shared
  +
b010 0 1 Reserved Reserved
  +
b010 1 X Reserved Reserved
  +
b1BB A A Cached memory; BB = outer policy, AA = inner policy [S]
   
  +
with the following encoding of Inner and Outer Cache Policy, when Most Significant Bit of TEX Is Set to 1:
''TEX:''
 
Type Extension field
 
   
  +
Memory Attribute Encoding (AA and BB) Cache Policy
These bits are implemented in the Cortex-M MPU Region Base Attribute and Size Register (0xE000EDA0):
 
  +
00 Noncacheable
<nowiki>
 
  +
01 Write back, write, and read allocate
31:29 Reserved
 
28 XN R/W Instruction Access Disable (1 = disable instruction fetch from this region; an attempt to do so will result in a memory management fault)
+
10 Write through, no write allocate
  +
11 Write back, no write allocate
27 Reserved
 
26:24 AP R/W — Data Access Permission field
 
23:22 Reserved
 
21:19 TEX R/W — Type Extension field
 
18 S R/W — Shareable
 
17 C R/W — Cacheable
 
16 B R/W — Bufferable
 
15:8 SRD R/W — Subregion disable
 
7:6 Reserved
 
5:1 REGION SIZE R/W — MPU Protection Region size
 
0 ENABLE R/W — Region enable
 
</nowiki>
 
 
<nowiki>
 
TEX C B Description Region Shareability
 
b000 0 0 Strongly ordered (transfers carry out and complete in programmed order) Shareable
 
b000 0 1 Shared device (write can be buffered) Shareable
 
b000 1 0 Outer and inner write-through; no write allocate [S]
 
b000 1 1 Outer and inner write-back; no write allocate [S]
 
b001 0 0 Outer and inner non cacheable [S]
 
b001 0 1 Reserved Reserved
 
b001 1 0 Implementation defined –
 
b001 1 1 Outer and inner write-back; write and read allocate [S]
 
b010 0 0 Nonshared device Not shared
 
b010 0 1 Reserved Reserved
 
b010 1 X Reserved Reserved
 
b1BB A A Cached memory; BB = outer policy, AA = inner policy [S]
 
</nowiki>
 
 
Encoding of Inner and Outer Cache Policy when Most Significant Bit of TEX Is Set to 1:
 
<nowiki>
 
Memory Attribute Encoding (AA and BB) Cache Policy
 
00 Noncacheable
 
01 Write back, write, and read allocate
 
10 Write through, no write allocate
 
11 Write back, no write allocate
 
</nowiki>
 
   
 
With embOS-MPU Cortex-M the ''Attributes'' parameter is shifted by 16 bits and set in the Cortex-M Region Base Attribute and Size Register.
 
With embOS-MPU Cortex-M the ''Attributes'' parameter is shifted by 16 bits and set in the Cortex-M Region Base Attribute and Size Register.
   
'''Example:'''
+
=== Example ===
<nowiki>
 
 
Setting the memory attribute of a region to Write back, no write allocate:
 
Setting the memory attribute of a region to Write back, no write allocate:
   
  +
<source lang="C">
 
#define TEX_100 (4u << 3)
 
#define TEX_100 (4u << 3)
 
#define CACHEABLE (1u << 1)
 
#define CACHEABLE (1u << 1)
Line 83: Line 80:
   
 
OS_MPU_AddRegion(&HPTask, 0x00, 0x2000, OS_MPU_READONLY, TEX_100 | BUFFERABLE | CACHEABLE);
 
OS_MPU_AddRegion(&HPTask, 0x00, 0x2000, OS_MPU_READONLY, TEX_100 | BUFFERABLE | CACHEABLE);
  +
</source>
 
</nowiki>
 

Revision as of 08:47, 1 April 2020

With embOS-MPU different memory regions with separate access rights and memory attributes can be defined. A memory region can be added with OS_MPU_AddRegion().

OS_MPU_AddRegion()

OS_MPU_AddRegion() has the following prototype:

void OS_MPU_AddRegion(OS_TASK* pTask,
                      OS_U32   BaseAddr,
                      OS_U32   Size,
                      OS_U32   Permissions,
                      OS_U32   Attributes);

ARMv7-M Memory Attributes

embOS-MPU includes defines for the permissions (e.g. OS_MPU_READONLY), but not for the attributes since they are core specific.

The Cortex-M memory attributes include the following bits:

Bufferable Write to memory can be carried out by a write buffer while the processor continues on next instruction execution.
Cacheable Data obtained from memory read can be copied to a memory cache so that next time it is accessed the value can be obtained from the cache to speed up the program execution.
Sharable Data in this memory region could be shared by multiple bus masters. Memory system needs to ensure coherency of data between different bus masters in shareable memory region.
TEX Type Extension field

These bits are implemented in the Cortex-M MPU Region Base Attribute and Size Register (0xE000EDA0):

31:29       Reserved
28          XN            R/W         — Instruction Access Disable (1 = disable instruction fetch from this region; an attempt to do so will result in a memory management fault)
27          Reserved
26:24       AP            R/W         — Data Access Permission field
23:22       Reserved
21:19       TEX           R/W         — Type Extension field
18          S             R/W         — Shareable
17          C             R/W         — Cacheable
16          B             R/W         — Bufferable
15:8        SRD           R/W         — Subregion disable
7:6         Reserved
5:1         REGION SIZE   R/W         — MPU Protection Region size
0           ENABLE        R/W         — Region enable

Permissible values are:

TEX  C B Description Region                                                         Shareability
b000 0 0 Strongly ordered (transfers carry out and complete in programmed order)    Shareable
b000 0 1 Shared device (write can be buffered)                                      Shareable
b000 1 0 Outer and inner write-through; no write allocate                           [S]
b000 1 1 Outer and inner write-back; no write allocate                              [S]
b001 0 0 Outer and inner non cacheable                                              [S]
b001 0 1 Reserved                                                                   Reserved
b001 1 0 Implementation defined                                                     –
b001 1 1 Outer and inner write-back; write and read allocate                        [S]
b010 0 0 Nonshared device Not shared
b010 0 1 Reserved                                                                   Reserved
b010 1 X Reserved                                                                   Reserved
b1BB A A Cached memory; BB = outer policy, AA = inner policy                        [S]

with the following encoding of Inner and Outer Cache Policy, when Most Significant Bit of TEX Is Set to 1:

Memory Attribute Encoding (AA and BB) Cache Policy
00                                    Noncacheable
01                                    Write back, write, and read allocate
10                                    Write through, no write allocate
11                                    Write back, no write allocate

With embOS-MPU Cortex-M the Attributes parameter is shifted by 16 bits and set in the Cortex-M Region Base Attribute and Size Register.

Example

Setting the memory attribute of a region to Write back, no write allocate:

#define TEX_100    (4u << 3)
#define CACHEABLE  (1u << 1)
#define BUFFERABLE (1u << 0)

OS_MPU_AddRegion(&HPTask, 0x00, 0x2000, OS_MPU_READONLY, TEX_100 | BUFFERABLE | CACHEABLE);