nRF51 Series Devices
SWDIO behavior on early batches
The SWDIO line on the nRF51822 series can be configured to also function as a reset pin if the SWDIO line is pulled LOW for more than 100us. After power on, the device is in normal mode where the reset functionality of the pin is enabled. As soon as activity on the SWCLK line is recognized, the device will enter debug interface mode where the reset functionality of SWDIO is disabled. For further information about the different modes, please refer to the reference manual of the device. On early batches of the nRF51822 series, the reset functionality was not correctly disabled when entering debug interface mode.
To check if a specific device is affected, the device printing needs to be checked. It is of the following format:
N51822 xxxxxx yyzzxx x = do not care y = Year or production zz = week of production
Devices produced before yy = 12, zz = 30 are affected by this problem.
Using J-Link SWD Isolator
As the J-Link SWD Isolator can only keep the last level of the SWDIO pin that was driven by one side, SWDIO may stay 0 between SWD sequences. This makes it impossible to use the J-Link SWD Isolator with these early batches of the device. Unfortunately, it is also not possible to disable the pin reset functionality manually on these early devices. Only devices produced at yy = 12, zz = 30 or later can be used with the J-Link SWD Isolator. Some very early devices do not even have N1822 or any date code on them. These are also affected by the pin reset problem.
Debugging on affected devices is only possible without using a J-Link SWD Isolator and when selecting the proper device in the debugger. Specifying the core only (Cortex-M0) won't work!