nRF91 Series Devices

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Tracing on Nordic Semiconductor nRF9160

This article describes how to get started with trace on the Nordic Semiconductor nRF9160 MCU. This article assumes that there is already a basic knowledge about trace in general (what is trace, what different implementations of trace are there, etc.). If this is not the case, we recommend to read Trace chapter in the J-Link User Manual (UM08001). The Nordic Semiconductor nRF9160 MCU implements tracing via pins and ETB, so J-Link Plus or higher can be used for ETB tracing and a J-Trace PRO for pin tracing. Examples for both types follow below.

Minimum requirements

In order to use trace on the Nordic Semiconductor nRF9160 MCU devices, the following minimum requirements have to be met:

  • J-Link software version V6.52 or later
  • Ozone V2.70 or later (if streaming trace and / or the sample project from below shall be used)
  • J-Trace PRO for Cortex-M HW version V1.0 or later for tracing via Pins, for the ETB example a J-Link Plus is sufficient
  • Tracepin connection like on the nRF9160-DK eval board

Sample projects

Streaming trace

The following sample project is designed to be used with J-Trace PRO and Ozone to demonstrate streaming trace. The project has been tested with the minimum requirements mentioned above and a nRF9160 DK board. The sample project comes with a pre-configured project file for Ozone that runs out-of-the box. In order to rebuild the sample project, SEGGER Embedded Studio can be used. The Ozone project will set two breakpoints, one after the trace init and one at main. This is needed due to some specifics of this device that are further explained in section Specifics/Limitations.

Nordic_nRF9160_Trace_Example.zip

ETB trace

The following sample project is designed to be used with J-Trace PRO and Ozone to demonstrate ETB trace. The project has been tested with the minimum requirements mentioned above and a nRF9160 DK board. The sample project comes with a pre-configured project file for Ozone that runs out-of-the box. In order to rebuild the sample project, SEGGER Embedded Studio can be used.

Nordic_nRF9160_ETB_Trace_Example.zip

Tested Hardware

nRF9160 DK

Specifics/Limitations

To be able to trace on the nRF91 DK eval board the 19-pin Debug In header must be soldered on.

Additionally the target specific trace init must be executed from within the application. This can usually be done via the trace probe with e.g. script file but in this case this is not possible due to the trace architecture of the nRF91 series. Thus trace must be enabled at startup of the application. The example application in this article comes with an excerpt form the Nordic SDK which takes care of this initialization. To enable it in your IDE the preprocessor option "ENABLE_TRACE" must be set. For more information see the Nordic SDK sources. Please note that this also means that trace information won't be available until the trace init code was executed so the data starting from the reset vector is missing.

Reference trace signal quality

The following pictures show oscilloscope measurements of trace signals output by the "Tested Hardware" using the example project. All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes. If your trace signals look similar on your trace hardware, chances are good that tracing will work out-of-the-box using the example project. More information about correct trace timing can be found at the following website.

Trace clock signal quality

The trace clock signal quality shows multiple trace clock cycles on the tested hardware as reference.

Trace clock signal quality

Rise time

The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1. For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal.

TCLK rise time

Setup time

The setup time shows the relative setup time between a trace data signal and trace clock. The measurement markers are set at 50% of the expected voltage level respectively. The following picture shows such a measurement for the trace data signal 0 relative to the trace clock signal.

TD0 setup time