J-Link High-Speed Sampling

SEGGER J-Link High-Speed Sampling (HSS) is an API provided as part of the J-Link SDK.

It can be used on devices which support reading/writing memory while the target is running (like ARM Cortex-M based devices). J-Link HSS allows high-speed sampling of target application variables via background access.

Use cases

J-Link HSS can be used for example by IDEs and users to display variables as graphs etc. with a high-resolution and without interfering with the target application’s real-time execution. It is used for such a purpose in multiple of SEGGERs applications, like J-Scope, Ozone or Embedded Studio.

Advantages of J-Link HSS vs ARM SWO

When using HSS instead of ARM’s SWO for high-speed sampling of target variables, there are a number of advantages for the user:

• SWO needs an additional pin for outputting the data to the debug probe. HSS uses the existing debug signals which are also used for regular debugging / memory accesses.
• When using SWO, the target needs to support specific hardware units that support periodic monitoring of certain target addresses (DWT units). For Cortex-M3/4, these are limited to 4, most Cortex-M0/M0+ targets do not even provide these units. When using J-Link HSS, no special hardware units need to be supported by the target.
• When using the DWT units of the target, to output sampling data via SWO, the SWO FIFO is easily overloaded, as soon as more than two 32-bit variables are sampled in parallel. Moreover, the DWT units are limited in flexibility. They can only sample 8-, 16- and 32-bit values. Longer variables or arrays cannot be monitored or will overload the SWO pin. HSS allows the user to configure flexible lengths of variables being monitored.
• When using SWO, target and debug probe need to use the same frequency for sending & receiving data which makes operation quite difficult, especially on targets where the target CPU speed changes dynamically. When using HSS, there are no such problems.